參數(shù)資料
型號(hào): IDT74FCT543ATPY8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 總線收發(fā)器
英文描述: FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: SSOP-24
文件頁(yè)數(shù): 1/7頁(yè)
文件大?。?/td> 75K
代理商: IDT74FCT543ATPY8
INDUSTRIALTEMPERATURERANGE
IDT74FCT543AT/CT/DT
FASTCMOSOCTALLATCHEDTRANSCEIVER
1
FEBRUARY 2006
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-5489/5
FEATURES:
A, C, and D grades
Low input and output leakage
≤≤≤≤≤1A (max.)
CMOS power levels
True TTL input and output compatibility:
–VOH = 3.3V (typ.)
–VOL = 0.3V (typ.)
High Drive outputs (-15mA IOH, 64mA IOL)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in SOIC, SSOP, and QSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT543AT/CT/DT
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
DESCRIPTION:
The FCT543T is a non-inverting octal transceiver built using an advanced
dual metal CMOS technology. This device contains two sets of eight D-type
latches with separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (
CEAB)inputmustbelowinorder
to enter data from A0–A7 or to take data from B0–B7, as indicated in the
Function Table. With
CEAB low, a low signal on the A-to-B Latch Enable
(
LEAB) input makes the A-to-B latches transparent; a subsequent low-to-
high transition of the
LEAB signal puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With
CEAB andOEAB both
low, the 3-state B output buffers are active and reflect the data present at the
output of the A latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
A 1
Q
OEBA
A 2
A 3
A 4
A 5
A 6
A 7
B 1
B 2
B 3
B 4
B 5
B 6
B 7
CEBA
LEB A
OEA B
CEA B
LEAB
DETAIL A x 7
D
LE
Q
D
LE
DETAIL A
A 0
B 0
相關(guān)PDF資料
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