參數(shù)資料
型號: IDT74FCT163646APFG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: TVSOP-56
文件頁數(shù): 7/8頁
文件大?。?/td> 199K
代理商: IDT74FCT163646APFG
7
IDT74FCT163646/A/C
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
Pulse
Generator
R T
D.U.T.
V CC
V IN
C L
V OUT
50pF
500
500
Open
GN D
6v
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
IN PU T
TIM IN G
IN PU T
ASYNCHRO NO US C O NTRO L
PR ES ET
CLEA R
ETC .
SYNCHRO N O US CO NTRO L
tSU
tH
tREM
tSU
tH
PR ES ET
CLEA R
C LO C K EN ABL E
ETC .
HIG H -LO W -H IG H
PU LS E
LO W -HIG H -LO W
PU LS E
tW
1.5V
SAM E PH A SE
IN PU T TR AN SITION
3V
1.5V
0V
1.5V
VOH
tPLH
OU TPU T
O PPO S ITE P H ASE
IN PU T TR AN SITION
3V
1.5V
0V
tPLH
tPH L
VOL
CO NT RO L
IN PU T
3V
1.5V
0V
3V
0V
OU TPU T
NO RM ALLY
LO W
OU TPU T
NO RM ALLY
HIG H
SW ITC H
6V
SW ITC H
GN D
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3V
0V
1.5V
EN AB LE
D ISA BLE
VOH
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
6V
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
3v16-link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If Vcc is below 3V, input voltage swings should be adjusted not to
exceed Vcc.
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