參數(shù)資料
型號(hào): IDT74FCT163543APA8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: TSSOP-56
文件頁數(shù): 1/7頁
文件大小: 86K
代理商: IDT74FCT163543APA8
1
IDT74FCT163543A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIALTEMPERATURERANGE
MAY 2002
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-3250/5
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended
Range
CMOS power levels (0.4
W typ. static)
Rail-to-rail output swing for increased noise margin
Low Ground Bounce (0.3V typ.)
Inputs (except I/O) can be driven by 3.3V or 5V components
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT163543A/C
3.3V CMOS 16-BIT
LATCHED TRANSCEIVER
DESCRIPTION:
The FCT163543 16-bit latched transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type latched transceivers with
separate input and output control to permit independent control of data flow
in either direction. For example, the A-to-B Enable (xCEAB) must be low
in order to enter data from the A port or to output data from the B port. xLEAB
controls the latch function. When xLEAB is low, the latches are transparent.
A subsequent low-to-high transition of xLEAB signal puts the A latches in
the storage mode. xOEAB performs output enable function on the B port.
Data flow from the B port to the A port is similar but requires using xCEBA,
xLEBA, and xOEBA inputs. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The FCT163543 have series current limiting resistors. These offer low
ground bounce, minimal undershoot, and controlled output fall times–
reducing the need for external series terminating resistors.
C
D
1
B1
1
LEAB
1
CEAB
1
OEAB
1
LEBA
1
CEBA
1
OEBA
TO SEVEN OTHER CHANNELS
1
A1
2
B1
2
LEAB
2
CEAB
2
OEAB
2
LEBA
2
CEBA
2
OEBA
TO SEVEN OTHER CHANNELS
2
A1
C
D
C
D
C
D
56
54
55
1
3
2
5
52
29
31
30
28
26
27
42
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