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參數(shù)資料
| 型號： | IDT72V845L15PFI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 4096X18 128QFP |
| 標準包裝： | 72 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲容量： | 72K（4K x 18） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 72V845L15PFI 800-2343 IDT72V845L15PFI-ND |
24
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009
Figure 30. Block Diagram of 8,192 x 18 Synchronous FIFO Memory with Programmable Flags
Used in Depth Expansion Configuration
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
Expansion using one IDT72V805/72V815/72V825/72V835/72V845s. Maxi-
mum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First Load (
FL)
control input.
2. All other devices must have
FL in the HIGH state.
3. The Write Expansion Out (
WXO) pin of each device must be tied to the
Write Expansion In (
WXI) pin of the next device. See Figure 30.
4. The Read Expansion Out (RXO) pin of each device must be tied to the
Read Expansion In (
RXI) pin of the next device. See Figure 30
5. All Load (
LD) pins are tied together.
6. The Half-Full flag (
HF) is not available in this Depth Expansion
Configuration.
7.
EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite
PAE
and
PAF flags are not precise.
8. In Daisy Chain mode, the flag outputs are single register-buffered and
the partial flags are in asynchronous timing mode.
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs
of one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 31 shows
a depth expansion using one IDT72V805/72V815/72V825/72V835/72V845
devices.
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next (“ripple down”) until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes LOW, enabling a write to the next FIFO in line.
LOAD
WRITE CLOCK
WRITE ENABLE
READ CLOCK
READ ENABLE
OUTPUT ENABLE
DATA IN
DATA OUT
RESET
FIRST LOAD (FL)
Vcc
WXOA
WXIA
RXOA
RXIA
WXOB
WXIB
RXOB
RXIB
IDT72V845
FFA/IRA
PAFA
EFA/ORA
PAEA
PAFB
PAEB
EF
PAE
FF
PAF
4295 drw 30
RCLKB
RENB
OEB
WCLKB
WENB
RSB
FLA
RCLKA
RENA
OEA
WCLKA
WENA
RSA
LDA
DAn
QAn
DBn
QBn
LDB
FIFO A
4,096 x 18
FIFO B
4,096 x 18
FFA/IRA EFA/ORA
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| IDT72V845L15PFI8 | 功能描述:IC FIFO SYNC 4096X18 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V845L20PF | 功能描述:IC FIFO SYNC 4096X18 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V845L20PF8 | 功能描述:IC FIFO SYNC 4096X18 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V84L15PA | 功能描述:IC FIFO ASYNCH 2048X18 56TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V84L15PA8 | 功能描述:IC FIFO ASYNCH 2048X18 56TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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