參數(shù)資料
型號(hào): IDT72V51456L6BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 39/57頁
文件大小: 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
標(biāo)準(zhǔn)包裝: 1
類型: 多隊(duì)列流量控制
安裝類型: 表面貼裝
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-BGA(17x17)
包裝: 托盤
其它名稱: 72V51456L6BB
44
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51436/72V51446/72V51456 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
RCLK
RADEN
Qout
REN
tAH
tAS
0001xxxx
RDADD
tA
NULL QUEUE
SELECT
*A*
*B*
*C*
*E*
*F*
tQH
tENS
Q1 Wn-3
Q1 Wn-2
Q1 Wn-1
tA
Q1 Wn
tA
Q4 W0
FWFT
OV
tROV
5935 drw23
SELECT
NEW QUEUE
*D*
00000100
tAH
tAS
tQH
tQS
tENH
tQS
Figure 20. Read Operation and Null Queue Select
NOTES:
1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words
from that queue.
2. Please see Figure 21, Null Queue Flow Diagram.
Cycle:
*A* Null Q of device 0 (32nd queue) is selected, when word Wn-1 from previously selected Q1 is read.
*B*
REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.
Note: *B* and *C* are a minimum 2 RCLK cycles between Q selects.
*C* The Null Q is seen as an empty queue on the read side, therefore Wn of Q1 remains in the O/P register and
OV goes HIGH.
*D* A new Q, Q4 is selected and the 1st word of Q4 will fall through present on the O/P register on cycle *F*.
5935 drw24
Queue 1
Memory
*A*
Null
Queue
*B*
Null
Queue
*C*
O/P Reg.
*D*
*E*
*F*
Null
Queue
Queue 4
Memory
Q1
Wn
Queue 4
Memory
O/P Reg.
Qn
Wn-1
Q1
Wn
Q1
Wn
Q1
Wn
Q1
Wn
Q1
Wn
Q1
Wn
Q4
W0
Q1
Wn
Q4
W1
Q4
W0
Figure 21. Null Queue Flow Diagram
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