參數(shù)資料
型號(hào)： IDT72V51446L7-5BBI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 45/57頁(yè)
文件大?。?/td> 0K
描述： IC FLOW CTRL MULTI QUEUE 256-BGA
標(biāo)準(zhǔn)包裝： 1
類型： 多隊(duì)列流量控制
安裝類型： 表面貼裝
封裝/外殼： 256-BBGA
供應(yīng)商設(shè)備封裝： 256-BGA（17x17）
包裝： 托盤
其它名稱： 72V51446L7-5BBI
5
IDT72V51436/72V51446/72V51456 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
single data output port with up to 16 FIFO queues in parallel buffering between
the two ports. The user can setup between 1 and 16 Queues within the device.
Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing
theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths,
independent of one another.
MEMORY ORGANIZATION/ ALLOCATION
The memory is organized into what is known as “blocks”, each block being
256x36bits.Whentheuserisconfiguringthenumberofqueuesandindividual
queue sizes the user must allocate the memory to respective queues, in units
of blocks, that is, a single queue can be made up from 0 to m blocks, where m
is the total number of blocks available within a device. Also the total size of any
given queue must be in increments of 256 x36. For the IDT72V51436,
IDT72V51446 and IDT72V51456 the Total Available Memory is 64, 128 and
256blocksrespectively(ablockbeing256x36).Queuescanbebuiltfromthese
blocks to make any size queue desired and any number of queues desired.
BUS WIDTHS
Theinputportiscommontoallqueueswithinthedevice,asistheoutputport.
ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport
and output port can be either x9, x18 or x36 bits wide provided that at least one
of the ports is x36 bits wide, the read and write port widths being set
independentlyofoneanother.Becausetheportsarecommontoallqueuesthe
width of the queues is not individually set, so that the input width of all queues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Data being written into the device via the input port is directed to a discrete
queue via the write queue select address inputs. Conversely, data being read
fromthedevicereadportisreadfromaqueueselectedviathereadqueueselect
addressinputs.Datacanbesimultaneouslywrittenintoandreadfromthesame
queue or different queues. Once a queue is selected for data writes or reads,
the writing and reading operation is performed in the same manner as a
conventional IDT synchronous FIFO, utilizing clocks and enables, there is a
single clock and enable per port. When a specific queue is addressed on the
write port, data placed on the data inputs is written to that queue sequentially
basedontherisingedgeofawriteclockprovidedsetupandholdtimesaremet.
Conversely, data is read on to the output port after an access time from a rising
edge on a read clock.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFO operating in standard IDT mode. Write operations can be performed on
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a queue is selected on the output port, the next word in that queue will
automaticallyfallthroughtotheoutputregister.Allsubsequentwordsfromthat
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
provides a user programmable almost full flag for all 16 queues and when a
respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.
The device provides a user programmable almost empty flag for all 16 queues
andwhenarespectivequeueisselectedonthereadport,thealmostemptyflag
provides status for that queue.
PROGRAMMABLE FLAG BUSSES
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost
full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 8 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within queues that may not be selected on the write or read port. As mentioned,
the device provides almost full and almost empty registers (programmable by
the user) for each of the 16 queues in the device.
In the IDT72V51436/72V51446/72V51456 multi-queue flow-control de-
vices the user has the option of utilizing anywhere between 1 and 16 queues,
therefore the 8 bit flag status busses are multiplexed between the 16 queues,
a flag bus can only provide status for 8 of the 16 queues at any moment, this
isreferredtoasa“Sector”,suchthatwhenthebusisprovidingstatusofqueues
1 through 8, this is sector 1, when it is queues 9 through 16, this is sector 2. If
less than 16 queues are setup in the device, there are still 2 sectors, such that
in “Polled” mode of operation the flag bus will still cycle through 2 sectors. If for
exampleonly14 queuesaresetup,sector1willreflectstatusofqueues1through
8. Sector 2 will reflect the status of queues 9 through 14 on the least significant
6 bits, the most significant 2 bits of the flag bus are don’t care.
The flag busses are available in two user selectable modes of operation,
“Polled” or “Direct”. When operating in polled mode a flag bus provides status
of each sector sequentially, that is, on each rising edge of a clock the flag bus
isupdatedtoshowthestatusofeachsectorinorder.Therisingedgeofthewrite
clockwillupdatethealmostfullbusandarisingedgeonthereadclockwillupdate
the almost empty bus. The mode of operation is always the same for both the
almost full and almost empty flag busses. When operating in direct mode, the
sector on the flag bus is selected by the user. So the user can actually address
the sector to be placed on the flag status busses, these flag busses operate
independently of one another. Addressing of the almost full flag bus is done via
the write port and addressing of the almost empty flag bus is done via the read
port.
PACKET MODE
The multi-queue flow-control device also offers a “Packet Mode” operation.
Packet Mode is user selectable and requires the device to be configured with
both write and read ports as 36 bits wide. In packet mode, users can define
the length of packets or frame by using the two most significant bits of the 36-
bit word. Bit 34 is used to mark the Start of Packet (SOP) and bit 35 is used to
mark the End of Packet (EOP) as shown in Table 5). When writing data into
a given queue, the first word being written is marked, by the user setting bit 34
as the “Start of Packet” (SOP) and the last word written is marked as the “End
of Packet” (EOP) with all words written between the Start of Packet (SOP)
marker (bit 34) and the End of packet (EOP) packet marker (bit 35) constituting
the entire packet. A packet can be any length the user desires, up to the total
available memory in the multi-queue flow-control device. The device monitors
the SOP (bit 34) and looks for the word that contains the EOP (bit 35). The read
port is supplied with an additional status flag, “Packet Ready”. The Packet
Ready (
PR)flaginconjunctionwithOutputValid(OV)indicateswhenatleast
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IDT72V51446L6BB IC FLOW CTRL MULTI QUEUE 256-BGA
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IDT72V51453L7-5BB8 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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