參數(shù)資料
型號: IDT72V51433L6BB8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 33/50頁
文件大?。?/td> 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
標準包裝: 1,000
類型: 多隊列流量控制
安裝類型: 表面貼裝
封裝/外殼: 256-BBGA
供應商設(shè)備封裝: 256-BGA(17x17)
包裝: 帶卷 (TR)
其它名稱: 72V51433L6BB8
39
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 20. Almost Empty Flag Timing and Queue Switch
Figure 21. Almost Empty Flag Timing
RCLK
RADEN
tQH
tQS
tAH
tAS
RDADD
D1 Q12
PAE
(Device 1)
tAELZ
5939 drw22
REN
tAH
tAS
tQH
tQS
tOLZ
Qout
tRAE
HIGH-Z
D1 Q15
PAE
(Device 2)
tAEHZ
HIGH
HIGH-Z
tA
D1 Q12 Wn
HIGH-Z
*B*
*C*
*E*
*F*
*D*
*A*
tA
D1 Q12 Wn+1
tA
D1 Q15 W0
tA
D1 Q15 W1
*G*
WCLK
tENH
tCLKH
tCLKL
WEN
PAE
RCLK
tENS
n+1 words in Queue
tRAE
tSKEW2
tRAE
12
REN
5939 drw23
tENS
tENH
n+2 words in Queue
n+1 words in Queue
Cycle:
*A* Queue 12 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The
PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* The
PAE flag output now switches to device 1. Word, Wn is read from Q12 due to the FWFT operation. This read operation from Q12 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*D* Q15 of device 1 is selected.
*E* The
PAE flag goes LOW due to the read from Q12 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*F* Word, W0 is read from Q15 due to the FWFT operation. The
PAE flag goes HIGH to show that Q15 is not almost empty.
NOTE:
1. The waveform here shows the
PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + tRAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.
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