參數(shù)資料
型號: IDT72V51236L6BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 39/56頁
文件大小: 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
標準包裝: 1
類型: 多隊列流量控制
安裝類型: 表面貼裝
封裝/外殼: 256-BBGA
供應商設備封裝: 256-BGA(17x17)
包裝: 托盤
其它名稱: 72V51236L6BB
44
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
WADEN
tQH
tQS
tAH
tAS
WRADD
D1 Q2
PAF
(Device 1)
tAFLZ
5937 drw25
WEN
tENS
tAH
tAS
tQH
tQS
tDH
tDS
WD-m
Din
tWAF
HIGH-Z
tENH
D1 Q0
PAF
(Device 2)
tFFHZ
1
2
D1 Q2
*B*
*C*
*E*
*F*
*D*
*A*
Figure 22. Almost Full Flag Timing and Queue Switch
Figure 23. Almost Full Flag Timing
WCLK
WEN
PAF
RCLK
tWAF
REN
5937 drw26
D - (m+1) words in Queue
D - m words in Queue
1
2
1
D-(m+1) words
in Queue
tWAF
tENH
tENS
tSKEW2
tENH
tENS
tCLKL
Cycle:
*A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The
PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* Word, Wd-m is written into Q2 causing the
PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + tWAF.
*D* Queue 0 if device 1 is now selected for write operations. This queue is not almost full, therefore the
PAF flag will update after a 2 WCLK + tWAF latency.
*E* The
PAF flag goes LOW based on the write 2 cycles earlier.
*F* The
PAF flag goes HIGH due to the queue switch to Q0.
NOTE:
1. The waveform here shows the
PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
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