IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
參數(shù)資料
型號: IDT72V3690L15PFI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 24/46頁
文件大?。?/td> 0K
描述: IC FIFO SS 32768X36 15NS 128TQFP
標準包裝: 36
系列: 72V
功能: 異步,同步
存儲容量: 1.1M(32K x 36)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 72V3690L15PFI
30
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
NOTES:
1. Retransmit setup is complete after
EF returns HIGH, only then can a read operation begin.
2.
OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore,
FF will be HIGH throughout the Retransmit setup procedure.
D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
tREF
tRTS
tENH
4667 drw16
tA
tENS
Wx
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q0 - Qn
tSKEW2
12
1
W1
tPAFS
tHF
tPAES
tREF
Wx+1
2
W2
tENH
WEN
tENS
tRTS
tENS
tENH
(3)
tA
(3)
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