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參數(shù)資料
| 型號(hào)： | IDT72V3641L20PQF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNCFIFO 1024X36 20NS 132PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲(chǔ)容量： | 36.8K（1K x 36） |
| 數(shù)據(jù)速率： | 520Mbs |
| 訪問時(shí)間： | 20ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 供應(yīng)商設(shè)備封裝： | 132-PQFP（24.13x24.13） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3641L20PQF |
12
COMMERCIALTEMPERATURERANGE
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO 512 x 36, 1,024 x 36 and 2,048 x 36
edge that takes the FIFO out of retransmit mode shifts the read pointer used by
the IR and
AF flagsfromtheshadowtothecurrentreadpointer. Ifthechange
of read pointer used by IR and
AF should cause one or both flags to transmit
HIGH, at least two CLKA synchronizing cycles are needed before the flags
reflect the change. A rising CLKA edge after the FIFO is taken out of retransmit
mode is the first synchronizing cycle of IR if it occurs at time tSKEW1 or greater
after the rising CLKB edge (see Figure 13). A rising CLKA edge after the FIFO
is taken out of retransmit mode is the first synchronizing cycle of
AFifitoccurs
at time tSKEW2 or greater after the rising CLKB edge (see Figure 14).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT72V3631/72V3641/72V3651 to
passcommandandcontrolinformationbetweenportAandportB. TheMailbox
select(MBA,MBB)inputschoosebetweenamailregisterandaFIFOforaport
datatransferoperation. ALOW-to-HIGHtransitiononCLKAwritesA0-A35data
to the mail1 register when a port-A Write is selected by
CSA, W/RA,andENA
withMBAHIGH. ALOW-to-HIGHtransitiononCLKBwritesB0-B35datatothe
mail2 register when a port-B Write is selected by
CSB, W/RB, and ENB with
MBB HIGH. Writing data to a mail register sets its corresponding flag (
MBF1
or
MBF2) LOW. Attempted writes to a mail register are ignored while its mail
flagisLOW.
Whentheport-Bdata(B0-B35)outputsareactive,thedataonthebuscomes
fromtheFIFOoutputregisterwhentheport-BMailboxselect(MBB)inputisLOW
and from the Mail1 register when MBB is HIGH. Mail2 data is always present
on the port-A data (A0-A35) outputs when they are active. The Mail1 register
Flag (
MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port-
BReadisselectedby
CSB,W/RB,andENBwithMBBHIGH. TheMail2register
Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port-
A Read is selected by
CSA, W/RA, and ENA with MBA HIGH. The data in a
mail register remains intact after it is read and changes only when new data is
writtentotheregister. MailRegisterandMailRegisterFlagtimingcanbefound
in Figure 15 and 16.
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| IDT72V3642L10PF | 功能描述:IC FIFO SYNC 3.3V CMOS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3642L10PF8 | 功能描述:IC FIFO 1MX72 10NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3642L10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 3.3V CMOS 120-TQFP |
| IDT72V3642L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 1MX72 10NS 120QFP |
| IDT72V3642L10PQF | 功能描述:IC FIFO 1MX72 10NS 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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