IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM
參數(shù)資料
型號： IDT72V36110L10PF8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 34/48頁
文件大?。?/td> 0K
描述： IC FIFO SYNC 131KX36 10NS 128QFP
標準包裝： 1,000
系列： 72V
功能： 同步
存儲容量： 4.7M（131K x 36）
數(shù)據(jù)速率： 166MHz
訪問時間： 10ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
其它名稱： 72V36110L10PF8
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
DESCRIPTION (CONTINUED)
Figure 1. Single Device Configuration Signal Flow Diagram
operation, which consists of activating
RENandenablingarisingRCLKedge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
RENdoes
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on
REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)and
PAF(ProgrammableAlmost-Fullflag). TheEFandFF
functions are selected in IDT Standard mode. The
IR and OR functions are
selected in FWFT mode.
HF, PAE and PAF are always available for use,
irrespective of timing mode.
PAE and PAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso
provided, so that
PAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the
PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring
Master Reset by the state of the FSEL0, FSEL1, and
LD pins.
For serial programming,
SEN together with LD on each rising edge of
WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,
WEN togetherwithLD oneachrisingedgeofWCLK,areused
to load the offset registers via Dn.
REN together with LD on each rising edge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serial or parallel offset loading has been selected.
During Master Reset (
MRS)thefollowingeventsoccur: thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming
modeandoffsetsineffect.
PRSisusefulforresettingadeviceinmid-operation,
when reprogramming programmable flags would be undesirable.
Itisalsopossibletoselectthetimingmodeofthe
PAE(ProgrammableAlmost-
Empty flag) and
PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the
PAEand
PAFflags.
BUS-
MATCHING
(BM)
(x36, x18 or x9) DATA OUT (Q0 - Qn)
(x36, x18 or x9) DATA IN (D0 - Dn)
MASTER RESET (MRS)
READ CLOCK (RCLK/RD*)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
WRITE CLOCK (WCLK/WR*)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72V36100
72V36110
PARTIAL RESET (PRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
6117 drw03
HALF-FULL FLAG (HF)
SERIAL ENABLE(SEN)
INPUT WIDTH (IW)
OUTPUT WIDTH (OW)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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IDT72V36110L15PF8 功能描述:IC FIFO SYNC 131KX36 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72V36110L15PFI 功能描述:IC FIFO SYNC 131KX36 15NS 128QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984
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