IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
參數(shù)資料
型號: IDT72V283L15PF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 26/45頁
文件大?。?/td> 0K
描述: IC FIFO 32768X18 15NS 80QFP
標(biāo)準(zhǔn)包裝: 45
系列: 72V
功能: 異步,同步
存儲容量: 589K(32K x 18)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-TQFP(14x14)
包裝: 托盤
其它名稱: 72V283L15PF
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
SEN
SI
4666 drw18
tENH
tENS
LD
tDS
BIT 0
EMPTY OFFSET
BIT X(1)
BIT 0
FULL OFFSET
tENH
tLDH
tDH
tLDH
BIT X(1)
tLDS
NOTES:
1. x9 to x9 mode: X = 9 for the IDT72V223, X = 10 for the IDT72V233, X = 11 for the IDT72V243, X = 12 for the IDT72V253, X = 13 for the IDT72V263, X = 14 for the IDT72V273,
X = 15 for the IDT72V283 and X = 16 for the IDT72V293.
2. All other modes: X = 8 for the IDT72V223, X = 9 for the IDT72V233, X = 10 for the IDT72V243, X = 11 for the IDT72V253, X = 12 for the IDT72V263, X = 13 for the IDT72V273,
X = 14 for the IDT72V283 and X = 15 for the IDT72V293.
tA
tRTS
tENH
4666 drw17
tENS
Wx
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q0 - Qn
tSKEW2
12
1
tPAFS
tHF
tPAES
Wx+1
2
W3
WEN
tENS
W2
(3)
4
5
tENH
W4
W5
(3)
3
W1
tA
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (
OR), will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore,
IR will be LOW throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263,
16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385
for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293.
3.
OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during
MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
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