IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM 65,536 x 9 " />
參數(shù)資料
型號: IDT72V281L10TF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 10/26頁
文件大小: 0K
描述: IC FIFO 32768X18 10NS 64QFP
標準包裝: 80
系列: 72V
功能: 同步
存儲容量: 589K(32K x 18)
數(shù)據(jù)速率: 100MHz
訪問時間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 72V281L10TF
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM
65,536 x 9 and 131,072 x 9
Figure
9.
Write
Timing
(First
Word
Fall
Through
Mode
)
NOTES:
1.
tSKEW3
is
the
minimum
time
between
a
rising
WCLK
edge
and
a
rising
RCLK
edge
to
guarantee
that
OR
will
go
LOW
after
two
RCLK
cycles
plus
t
REF
.If
the
time
between
the
rising
edge
of
WCLK
and
the
rising
edge
of
RCLK
is
less
than
tSKEW3
,then
OR
assertion
may
be
delayed
one
extra
RCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
WCLK
edge
and
a
rising
RCLK
edge
to
guarantee
that
PAE
will
go
HIGH
after
one
RCLK
cycle
plus
t
PAE
.If
the
time
between
the
rising
edge
of
WCLK
and
the
rising
edge
of
RCLK
is
less
than
tSKEW2
,then
the
PAE
deassertion
may
be
delayed
one
extra
RCLK
cycle.
3.
LD
=
HIGH,
OE
=
LOW
4.
n=
PAE
offset,
m
=
PAF
offset
and
D
=
maximum
FIFO
depth.
5.
D
=
65,537
for
the
IDT72V281
and
131,073
for
the
IDT72V291.
6.
First
data
word
latency:
60ns
+
t
REF
+
2*T
RCLK
.
W
1
W
2
W
4
W
[n
+2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D
0
-
D
8
RCLK
tDH
tDS
tENS
tSKEW3
(1)
REN
Q
0
-Q
8
PAF
HF
PAE
IR
tDS
tSKEW2
tA
tREF
OR
tPAE
tHF
tPAF
tWFF
W
[D-m+2]
W
1
tENH
4513
drw
12
DATA
IN
OUTPUT
REGISTER
(2)
W
3
1
2
3
1
D-1
]
[
W
D-1
]
[
W
D-1
]
[
W
1
2
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