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參數(shù)資料
| 型號： | IDT72V261LA10PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SS 8192X18 10NS 64QFP |
| 標準包裝： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 144K（8K x 18） |
| 數(shù)據速率： | 100MHz |
| 訪問時間： | 10ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V261LA10PF8 |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 and 32,768 x 9
24
JANUARY 30, 2009
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
WRITE CLOCK (WCLK)
m + n
m
n
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72V261LA
72V271LA
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PARTIAL RESET (PRS)
IDT
72V261LA
72V271LA
4673 drw 22
FULL FLAG/INPUT READY (FF/IR) #2
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the
control signals of multiple devices. Status flags can be detected from
any one device. The exceptions are the
EF and FF functions in IDT
Standard mode and the
IR and OR functions in FWFT mode. Because
of variations in skew between RCLK and WCLK, it is possible for
EF/FF
deassertion and
IR/OR assertion to vary by one cycle between FIFOs.
In IDT Standard mode, such problems can be avoided by creating
Figure 19. Block Diagram of 16,384 x 18 and 32,768 x 18 Width Expansion
composite flags, that is, ANDing
EF of every FIFO, and separately
ANDing
FF of every FIFO. In FWFT mode, composite flags can be
created by ORing
OR of every FIFO, and separately ORing IR of every
FIFO.
Figure 21 demonstrates a width expansion using two IDT72V261LA/
72V271LA devices. D0 - D8 from each device form a 18-bit wide input
bus and Q0-Q8 from each device form a 18-bit wide output bus. Any
word width can be attained by adding additional IDT72V261LA/72V271LA
devices.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V261LA10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X18 10NS 64TQFP 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 144K 16KX9 3.3V TQFP64 制造商:Integrated Device Technology Inc 功能描述:IC, FIFO, 144K, 16KX9, 3.3V, TQFP64 |
| IDT72V261LA10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X18 10NS 64TQFP |
| IDT72V261LA10TF | 功能描述:IC FIFO SS 8192X18 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V261LA10TF8 | 功能描述:IC FIFO SS 8192X18 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V261LA10TFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X18 10NS 64QFP |
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