參數(shù)資料
型號: IDT72T7295L10BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 13/53頁
文件大?。?/td> 0K
描述: IC FIFO 32768X72 10NS 324-BGA
標準包裝: 1
系列: 72T
訪問時間: 10ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 324-BGA
供應商設備封裝: 324-PBGA(19x19)
包裝: 托盤
其它名稱: 72T7295L10BB
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
Onceamarkedlocationhasbeenset(andthedeviceisstillinretransmitmode,
MARK is HIGH), a retransmit can be initiated by a rising RCLK edge while the
retransmit input (
RT) is LOW. REN must be HIGH (reads disabled) before
bringing
RTLOW.Thedeviceindicatesthestartofretransmitsetupbysetting
OR HIGH.
When
OR goes LOW, retransmit setup is complete and on the next rising
RCLK edge after retransmit setup is complete, (
RTgoesHIGH),thecontents
of the first retransmit location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of
REN, a
LOW on
RENis not required for the first word. Reading all subsequent words
requires a LOW on
REN to enable the rising RCLK edge. See Figure 19,
Retransmit from Mark timing (FWFT mode), for the relevant timing diagram.
Note, there must be a minimum of 32 bytes of data between the write pointer
and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long
words).Also,oncetheMARKisset,thewritepointerwillnotincrementpastthe
“marked” location until the MARK is deasserted. This prevents “overwriting” of
retransmitdata.
HSTL/LVTTL I/O
BoththewriteportandreadportareuserselectablebetweenHSTLorLVTTL
I/O, via two select pins, WHSTL and RHSTL respectively. All other control pins
are selectable via SHSTL, see Table 5 for details of groupings.
Note,thatwhenthewriteportisselectedforHSTLmode,theusercanreduce
the power consumption (in stand-by mode by utilizing the
WCS input).
All “Static Pins” must be tied to VCC or GND. These pins are LVTTL only,
and are purely device configuration pins.
WHSTL SELECT
RHSTL SELECT
SHSTL SELECT
STATIC PINS
WHSTL: HIGH = HSTL
RHSTL: HIGH = HSTL
SHSTL: HIGH = HSTL
LVTTL ONLY
LOW = LVTTL
Dn (I/P)
RCLK/RD (I/P)
EF/OR (O/P)
SCLK (I/P)
PRS (I/P)
IW (I/P)
OW (I/P)
WCLK/WR (I/P)
RCS (I/P)
PAF (O/P)
LD (I/P)
TRST (I/P)
BM (I/P)
ASYW (I/P)
WEN (I/P)
MARK (I/P)
EREN (O/P)
MRS (I/P)
TDI (I/P)
ASYR (I/P)
BE (I/P)
WCS (I/P)
REN (I/P)
PAE (O/P)
TCK (I/P)
IP (I/P)
FSEL0 (I/P)
OE (I/P)
FF/IR (O/P)
TMS (I/P)
FSEL1 (I/P)
PFM (I/P)
RT (I/P)
HF (O/P)
SEN (I/P)
SHSTL (I/P)
WHSTL (I/P)
Qn (O/P)
ERCLK (O/P)
FWFT/SI (I/P)
RHSTL (I/P)
TDO (O/P)
TABLE 5 — I/O CONFIGURATION
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