參數(shù)資料
型號(hào)： IDT72T72115L6-7BB
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 50/53頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 131072X72 6-7NS 324-BGA
標(biāo)準(zhǔn)包裝： 1
系列： 72T
訪問(wèn)時(shí)間： 3.8ns
電源電壓： 2.375 V ~ 2.625 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 324-BGA
供應(yīng)商設(shè)備封裝： 324-PBGA（19x19）
包裝： 托盤
其它名稱： 72T72115L6-7BB
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
PIN DESCRIPTION
Symbol
Name
I/O TYPE
Description
ASYR(1) Asynchronous
LVTTL
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port
INPUT
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
ASYW(1) Asynchronous
LVTTL
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
WritePort
INPUT
will select Asynchronous operation.
BE(1)
Big-Endian/
LVTTL
During Master Reset, a LOW on
BE will select Big-Endian operation. A HIGH on BE during Master Reset
Little-Endian
INPUT
willselectLittle-Endianformat.
BM(1)
Bus-Matching
LVTTL
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
INPUT
configuration.
D0–D71 DataInputs
HSTL-LVTTL Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins are in a don’t care
INPUT
state.
EF/OR
Empty Flag/
HSTL-LVTTL In the IDT Standard mode, the
EFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.
Output Ready
OUTPUT
In FWFT mode, the
OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
ERCLK RCLK Echo
HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
EREN
Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
FF/IR
Full Flag/
HSTL-LVTTL In the IDT Standard mode, the
FF function is selected. FF indicates whether or not the FIFO memory is
Input Ready
OUTPUT
full. In the FWFT mode, the
IR function is selected. IR indicates whether or not there is space available for
writing to the FIFO memory.
FSEL0(1) Flag Select Bit 0
LVTTL
During Master Reset, this input along with FSEL1 and the
LD pin, will select the default offset values for the
INPUT
programmable flags
PAE and PAF. There are up to eight possible settings available.
FSEL1(1) Flag Select Bit 1
LVTTL
During Master Reset, this input along with FSEL0 and the
LD pin will select the default offset values for the
INPUT
programmable flags
PAE and PAF. There are up to eight possible settings available.
FWFT/
First Word Fall
HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
SI
Through/Serial In
INPUT
functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be set-up in IDT Standard mode.
HF
Half-Full Flag
HSTL-LVTTL
HF indicates whether the FIFO memory is more or less than half-full.
OUTPUT
IP(1)
Interspersed Parity
LVTTL
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
INPUT
Parity mode.
IW(1)
InputWidth
LVTTL
This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.
INPUT
LD
Load
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the
LD input along with FSEL0 and FSEL1,
INPUT
determines one of eight default offset values for the
PAEandPAFflags,alongwiththemethodbywhichthese
offsetregisterscanbeprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswriting
to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR
READ DATA TO/FROM THE FIFO MEMORY.
MARK
Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
INPUT
operation will reset the read pointer to this position.
MRS
Master Reset
HSTL-LVTTL
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
INPUT
Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
Synchronous/Asynchronousoperationofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,
serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatencytimingmode,
interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
OE
OutputEnable
HSTL-LVTTL
OE provides Asynchronous three-state control of the data outputs, Qn.During a Master or Partial Reset the
INPUT
OE input is the only input that provide High-Impedance control of the data outputs.
OW(1)
OutputWidth
LVTTL
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
INPUT
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