參數(shù)資料
型號： IDT72T3695L4-4BB
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 52/57頁
文件大?。?/td> 0K
描述： IC FIFO 32768X36 4-4NS 208BGA
標準包裝： 1
系列： 72T
功能： 異步，同步
存儲容量： 1.1M（32K x 36）
數(shù)據(jù)速率： 100MHz
訪問時間： 3.4ns
電源電壓： 2.375 V ~ 2.625 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 208-BGA
供應(yīng)商設(shè)備封裝： 208-PBGA（17x17）
包裝： 托盤
其它名稱： 72T3695L4-4BB
56
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T3645 can easily be adapted to applications requiring depths
greater than 1,024, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665,
8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the
IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115
and 262,144 for the IDT72T36125 with an 18-bit bus width. In FWFT mode,
theFIFOscanbeconnectedinseries(thedataoutputsofoneFIFOconnected
to the data inputs of the next) with no external logic necessary. The resulting
configuration provides a total depth equivalent to the sum of the depths
associated with each single FIFO. Figure 37 shows a depth expansion using
two IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the
datawordappearsattheoutputsofoneFIFO,thatdevice's
ORlinegoesLOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for
ORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock, for the
OR flag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFO of the chain, that FIFO's
IRlinegoesLOW,enablingtheprecedingFIFO
to write a word to fill it.
Forafullexpansionconfiguration,theamountoftimeittakesfor
IRofthefirst
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock, for the
IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
end of the chain and free locations to the beginning of the chain.
Figure 37. Block Diagram of 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36, 262,144 x 36 and 524,288 x 36
Depth Expansion
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
5907 drw42
n
FWFT/SI
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
RCS
READ CHIP SELECT
RCS
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
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IDT72T3695L5BBI 功能描述:IC FIFO 32768X36 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T3695L6-7BB 功能描述:IC FIFO 32768X36 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T40108L10BB 功能描述:IC FIFO DDR/SDR 10NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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