IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
參數資料
型號： IDT72T1895L4-4BB
廠商： IDT, Integrated Device Technology Inc
文件頁數： 49/55頁
文件大?。?/td> 0K
描述： IC FIFO 65536X18 4NS 144BGA
標準包裝： 1
系列： 72T
功能： 異步，雙端口
存儲容量： 1.1M（65K x 18）
數據速率： 10MHz
訪問時間： 3.4ns
電源電壓： 2.375 V ~ 2.625 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 144-BGA
供應商設備封裝： 144-PBGA（13x13）
包裝： 托盤
其它名稱： 72T1895L4-4BB
53
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
WRITE CLOCK (WCLK)
m + n
mn
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PARTIAL RESET (PRS)
5909 drw40
FULL FLAG/INPUT READY (FF/IR) #2
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
READ CHIP SELECT (RCS)
SERIAL CLOCK (SCLK)
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the
EFandFF functionsinIDTStandardmodeandtheIR
and
ORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
and WCLK, it is possible for
EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing
EF of every FIFO, and
separately ANDing
FFofeveryFIFO. InFWFTmode,compositeflagscanbe
created by ORing
OR of every FIFO, and separately ORing IRof every FIFO.
Figure 36 demonstrates a width expansion using two IDT72T1845/
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125 devices. D0 - D17 from each device form a 36-bit wide input bus and
Q0-Q17 from each device form a 36-bit wide output bus. Any word width can
be attained by adding additional IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125 devices.
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of Width Expansion
For the x18 Input or x18 Output bus Width: 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 18, 32,768 x 18, 65,536 x 36, 131,072 x 36,
262,144 x 36 and 524,288 x 36
For both x9 Input and x9 Output bus Widths: 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18,
524,288 x 18 and 1,048,576 x 18
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相關代理商/技術參數
參數描述
IDT72T1895L4-4BBG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X18 4NS 144BGA
IDT72T1895L4-4BBG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X18 4NS 144BGA
IDT72T1895L5BB 功能描述:IC FIFO 65536X18 5NS 144BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數據速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T1895L5BBGI 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X18 5NS 144BGA
IDT72T1895L5BBGI8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X18 5NS 144BGA
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