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參數(shù)資料
| 型號： | IDT72T1885L6-7BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 44/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 32768X18 6-7NS 144BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，雙端口 |
| 存儲容量： | 589K（32K x 18） |
| 數(shù)據(jù)速率： | 10MHz |
| 訪問時間： | 3.8ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應(yīng)商設(shè)備封裝： | 144-PBGA（13x13） |
| 包裝： | 托盤 |
| 其它名稱： | 72T1885L6-7BB |
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49
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
Qn
O/P
Reg.
tA
tREF
OR
5909 drw33
tRCSLZ
REN
t
tENH
RCS
tENS
RCLK
a
b
c
d
e
f
g
h
i
Wn+1
WCLK
WEN
D0 - Dn
tSKEW1
tENS
tDS
tENH
Wn+2
Wn+3
ERCLK
EREN
tCLKEN
Wn+1
Wn+2
Wn+3
tA
tREF
Wn+1
Wn+2
Wn+3
tA
Wn Last Word
tA
tDH
tDS
1
2
tERCLK
HIGH-Z
Figure 29. Echo RCLK and Echo
REN
REN Operation (FWFT Mode Only)
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when
RCS and OE are both active, LOW, that is the bus is not in High-
Impedance state.
2.
OE is LOW.
Cycle:
a&b. At this point the FIFO is empty,
OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c.
Word Wn+1 falls through to the output register,
OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
d.
EREN goes HIGH, no new word has been placed on the output register on this cycle.
e.
No Operation.
f.
RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take
RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
g.
REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
h.
Word Wn+3 is read out,
EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
i.
This is the next enabled read after the last word, Wn+3 has been read out.
OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
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| IDT72T1895L4-4BB | 功能描述:IC FIFO 65536X18 4NS 144BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T1895L4-4BBG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X18 4NS 144BGA |
| IDT72T1895L4-4BBG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X18 4NS 144BGA |
| IDT72T1895L5BB | 功能描述:IC FIFO 65536X18 5NS 144BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T1895L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X18 5NS 144BGA |
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