參數(shù)資料
型號: IDT728985J8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/13頁
文件大?。?/td> 0K
描述: IC DGTL SW 256X256 44-PLCC
標(biāo)準(zhǔn)包裝: 450
系列: 7200
類型: 多路復(fù)用器
電路: 1 x 8:8
獨立電路: 1
電壓電源: 單電源
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
其它名稱: 728985J8
2
Commercial Temperature Range
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
35
34
33
32
31
30
29
37
36
3
2
44
1
43
42
41
5
4
6
5708 drw02
INDEX
38
39
40
21
22
24
23
25
26
27
19
20
18
28
DS
CS
R/
W
11
12
13
14
15
16
17
9
10
8
7
RX2
RX1
RX0
DTA
TX0
TX1
TX2
DNC
(1)
CCO
ODE
TX3
TX4
TX5
TX6
TX7
GND
D0
RX3
RX4
RX5
RX6
RX7
VCC
F0i
C4i
A0
D1
D2
D3
D4
A1
A2
DNC
(1)
DNC
(1)
DNC
(1)
D
5
D
6
D
7
A
5
A
4
A
3
DTA
CCO
ODE
1
2
40
39
TX0
3
38
TX1
4
37
TX2
5
36
TX3
6
35
TX4
7
34
TX5
8
33
TX6
9
32
TX7
10
31
GND
11
30
D0
12
29
CS
13
28
14
27
5708 drw04
15
16
17
18
19
20
26
25
24
23
22
21
RX1
RX2
RX3
RX4
RX5
RX6
F0i
A0
R/
W
DS
C4i
VCC
RX7
RX0
D1
D2
D3
D4
D5
D6
D7
A1
A2
A3
A4
A5
PIN CON.IGURATION
PIN DESCRIPTIONS
PLCC: 0.05in. pitch, 0.65in. x 0.65in.
(J44-1, order code: J)
TOP VIEW
PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in.
(P40-1, order code: P)
TOP VIEW
29
28
27
26
25
24
23
31
30
44
43
42
41
5708 drw03
INDEX
32
33
40
DS
CS
R/
W
5
6
7
8
9
10
11
3
4
2
1
RX2
RX1
RX0
DTA
TX0
TX1
TX2
DNC
(1)
CCO
ODE
TX3
TX4
TX5
TX6
TX7
GND
D0
RX3
RX4
RX5
RX6
RX7
VCC
F0i
C4i
A0
D1
D2
D3
D4
A1
A2
DNC
(1)
DNC
(1)
DNC
(1)
D
5
D
6
D
7
A
5
A
4
A
3
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
NOTE:
1. DNC - Do Not Connect
SYMBOL
NAME
I/O
DESCRIPTION
GND
Ground.
Ground Rail.
VCC
+5.0 Volt Power Supply.
DTA
Data Acknowledgment
O
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
(Open Drain)
output.
RX0-7
RX Input 0 to 7
I
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
F0i
Frame Pulse
I
This input accepts and automatically identifies frame synchronization signals formatted according to different
backplane specifications such as ST-BUS and GCI.
C4i
Clock
I
4.096 MHz serial clock for shifting data in and out of the data streams.
A0-A5
Address 0 to 5
I
These lines provide the address to IDT728985 internal registers.
DS
Data Strobe
I
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
R/
W
Read/Write
I
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
CS
Chip Select
I
Active LOW input enabling a microprocessor read or write of control register or internal memories.
D0-D7
Data Bus 0 to 7
I/O
These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
TX0-7
TX Outputs 0 to 7
O
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
(Three-state Outputs)
ODE
Output Drive Enable
I
This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
CCO
Control Channel Output
O
This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the
contents of the CCO bit in the Connection Memory HIGH locations.
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