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參數(shù)資料
| 型號： | IDT728980J8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 256X256 44-PLCC |
| 標準包裝： | 450 |
| 系列： | 7200 |
| 類型： | 多路復用器 |
| 電路： | 1 x 8:8 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應商設備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 728980J8 |
4
Commercial Temperature Range
IDT728980 Time Slot Interchange
Digital Switch 256 x 256
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)
or disables (if LOW) the output stream and channel.
Thecontentsofbit1(CCO)ofeachConnectionMemoryHighLocation(see
Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/s
output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on
CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the
CCOoutputistransmittedinLOW. Thecontentsofthe256CCObitsoftheCMH
are transmitted sequentially on to the CCO output pin and are synchronous to
the TX streams. To allow for delay in any external control circuitry the contents
of the CCO bit is output one channel before the corresponding channel on the
TXstreams. Forexample,thecontentsofCCObitinposition0(corresponding
to TX0, CH0) is transmitted synchronously with the TX channel 31, bit 7. Bit 1's
of CMH for channel 1 of stream 0-7 are output synchronously with TX channel
0 bits 7-0.
Table 2. Address Mapping
Connection Memory High
Connection Memory Low
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
100001
100010
111111
Data Memory
0
1
0
1
0
2
0
1
3
1
0
4
1
0
1
5
1
0
6
1
7
Stream
0
1
0
1
Control Register
CRb7
External Address Bits
A5-A0
5706 drw07
100000
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable via
A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
CRb6CRb5CRb4CRb3CRb2CRb1CRb0
CRb4CRb3
CRb2CRb1CRb0
Table 1. Input Stream to Output Stream Combinations that can Provide the
Minimum 2-Channel Delay
Figure 3.
Address Mapping
Input
Output Stream
0
1,2,3,4,5,6,7
1
3,4,5,6,7
2
5,6,7
37
4
1,2,3,4,5,6,7
5
3,4,5,6,7
6
5,6,7
77
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
A5 A4 A3 A2 A1 A0
HEX ADDRESS
LOCATION
0
XXXXX
00-1F
Control Register(1)
100000
20
Channel 0(2)
100001
21
Channel 1(2)
111111
3F
Channel 31(2)
INITIALIZATION OF THE IDT728980
On initialization or power up, the contents of the Connection Memory High
can be in any state. This is a potentially hazardous condition when multiple TX
outputs are tied together to form matrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
programthedesiredactivepathsthroughthematrices,andputallotherchannels
into the high impedance state. Care should be taken that no two connected TX
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
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