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參數(shù)資料
| 型號： | IDT72403L35SO8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO PAR 64X4 35NS 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 異步 |
| 存儲容量： | 256（64 x 4） |
| 訪問時間： | 35ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72403L35SO8 |
5
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
JUNE 29, 2012
FUNCTIONALDESCRIPTION
The 64x4FIFOisdesigned usinga dual port RAMarchitecture asopposed
to the traditional shift register approach. This FIFO architecture has a write
pointer, a read pointer and control logic, which allow simultaneous read and
writeoperations. ThewritepointerisincrementedbythefallingedgeoftheShift
In(Sl)control;thereadpointerisincrementedbythefallingedgeoftheShiftOut
(SO). The Input Ready (IR) signals when the FIFO has an available memory
location; Output Ready (OR) signals when there is valid data on the output.
OutputEnable(OE)providesthecapabilityofthree-statingtheFIFOoutputs.
FIFO RESET
TheFIFOmustberesetuponpowerupusingtheMasterReset(MR)signal.
ThiscausestheFlFOtoenteranemptystate,signifiedbyOutputReady(OR)
being LOW and Input Ready (IR) being HIGH. In this state, the data outputs
(Q0-3) will be LOW.
DATAINPUT
DataisshiftedinontheLOW-to-HlGHtransitionofShiftIn(Sl).Thisloads
inputdataintothefirstwordlocationoftheFIFOandcausesInputReady(IR)
togoLOW.OntheHlGH-to-LOWtransitionofSI,thewritepointerismovedto
thenextwordpositionandIRgoesHIGH,indicatingthereadinesstoacceptnew
data. If the FIFO is full, IR will remain LOW until a word of data is shifted out.
DATAOUTPUT
DataisshiftedoutontheHlGH-to-LOWtransitionofShiftOut(SO). Thiscauses
the internal read pointer to be advanced to the next word location. If data is
present, valid data will appear on the outputs and Output Ready (OR) will go
HIGH. Ifdataisnotpresent,ORwillstayLOWindicatingtheFIFOisempty. The
lastvalidwordreadfromtheFIFOwillremainattheFlFOsoutputwhenitisempty.
WhentheFIFOisnotempty,ORgoesLOWontheLOW-to-HIGHtransitionof
SO. PreviousdataremainsontheoutputuntiltheHIGH-to-LOWtransitionof
SO).
FALL THROUGH MODE
TheFIFOoperatesinafall-throughmodewhendatagetsshiftedintoanempty
FIFO. Afterafall-throughdelaythedatapropagatestotheoutput. Whenthe
datareachestheoutput,theOutputReady(OR)goesHIGH. Fall-throughmode
alsooccurswhentheFIFOiscompletelyfull. Whendataisshiftedoutofthefull
FIFO,alocationisavailablefornewdata. Afterafall-throughdelay,theInput
Ready (IR) goes HIGH. If Shift In (SI) is HIGH, the new data can be written
to the FIFO.
SincetheseFlFOsarebasedonaninternaldual-portRAMarchitecturewith
separatereadandwritepointers,thefall-throughtime(tPT)isonecyclelong.
AwordmaybewrittenintotheFIFOonaclockcycleandcanbeaccessedon
thenextclockcycle.
Figure 3. The Mechanism of Shifting Data Into the FIFO
NOTES:
1. IR HIGH indicates space is available and a SI pulse may be applied.
2. Input Data is loaded into the first word.
3. IR goes LOW indicating the first word is full.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full then the IR remains LOW.
7. SI pulses applied while IR is LOW will be ignored (see Figure 4).
Figure 2. Input Timing
SI
IR
INPUT DATA
2747 drw 06
1/fIN
tSIH
tSIL
tIDH
tIDS
1/fIN
tIRH
tIRL
SI
IR
INPUT DATA
STABLE DATA
(2)
(3)
(5)
2747 drw 07
(6)
(4)
(1)
(7)
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