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參數(shù)資料
| 型號： | IDT723662L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO BI SYNC 8192X36 120QFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 288K（8K x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723662L15PF8 |
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11
COMMERCIALTEMPERATURERANGE
IDT723652/723662/723672 CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
for the IDT723652, IDT723662, or IDT723672, respectively. The highest
numbered input is used as the most significant bit of the binary number in each
case. Validprogrammingvaluesfortheregistersrangesfrom1to2,044forthe
IDT723652; 1 to 4,092 for the IDT723662; and 1 to 8,188 for the IDT723672.
After all the offset registers are programmed from port A, the port B Full/Input
Ready flag (
FFB/IRB) is set HIGH, and both FIFOs begin normal operation.
See Figure 3 for relevant offset register parallel programming timing diagram.
FIFO WRITE/READ OPERATION
ThestateoftheportAdata(A0-A35)outputsiscontrolledbyportAChipSelect
(
CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are in the
high-impedancestatewheneither
CSAorW/RAisHIGH. TheA0-A35outputs
are active when both
CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is
LOW, and
FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when
CSAisLOW,W/RAisLOW,ENA
is HIGH, MBA is LOW, and
EFA/ORAisHIGH(seeTable2). FIFOreadsand
writes on port A are independent of any concurrent port B operation. Write and
Read cycle timing diagrams for Port A can be found in Figure 4 and 7.
The port B control signals are identical to those of port A with the exception
thattheportBWrite/Readselect(
W/RB)istheinverseoftheportAWrite/Read
select(W/
RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe
port B Chip Select (
CSB) and port B Write/Read select (W/RB). The B0-B35
outputs are in the high-impedance state when either
CSB is HIGH orW/RBis
LOW. The B0-B35 outputs are active when
CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transitionofCLKBwhen
CSBisLOW,W/RBisLOW,ENBisHIGH,MBBisLOW,
and
FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a
LOW-to-HIGH transition of CLKB when
CSB is LOW, W/RB is HIGH, ENB is
HIGH, MBB is LOW, and
EFB/ORB is HIGH (see Table 3). FIFO reads and
writes on port B are independent of any concurrent port A operation. Write and
Read cycle timing diagrams for Port B can be found in Figure 5 and 6.
ThesetupandholdtimeconstraintstotheportClocksfortheportChipSelects
andWrite/Readselectsareonlyforenablingwriteandreadoperationsandare
notrelatedtohigh-impedancecontrolofthedataoutputs. IfaportenableisLOW
during a clock cycle, the port’s Chip Select and Write/Read select may change
states during the setup and hold time window of the cycle.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, the first word will cause
the Empty Flag to change state on the second LOW-to-HIGH transition of the
Read Clock. The data word will not be automatically sent to the output register.
Instead, data residing in the FIFO's memory array is clocked to the output
register only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Function
H
X
High-Impedance
None
L
X
Input
None
LL
H
L
↑
Input
FIFO2 write
LL
H
↑
Input
Mail2 write
L
H
L
X
Output
None
LH
H
L
↑
Output
FIFO1 read
L
H
L
H
X
Output
None
LH
H
↑
Output
Mail1 read (set
MBF1 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
W/
RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Function
H
X
High-Impedance
None
L
H
L
X
Input
None
LH
H
L
↑
Input
FIFO1 write
LH
H
↑
Input
Mail1 write
L
X
Output
None
LL
H
L
↑
Output
FIFO2 read
L
H
X
Output
None
LL
H
↑
Output
Mail2 read (set
MBF2 HIGH)
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| IDT723662L15PQF | 功能描述:IC FIFO BI SYNC 8192X36 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723663L12PF | 功能描述:IC FIFO SYNC 4096X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723663L12PF8 | 功能描述:IC FIFO SYNC 4096X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723663L15PF | 功能描述:IC FIFO SYNC 4096X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723663L15PF8 | 功能描述:IC FIFO SYNC 4096X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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