參數(shù)資料
型號： IDT723624L12PFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 34/35頁
文件大?。?/td> 0K
描述： IC FIFO 256X36X2 SYNC 128TQFP
標(biāo)準(zhǔn)包裝： 72
系列： 7200
功能： 同步
存儲容量： 18.4K（256 x 36 x 2）
數(shù)據(jù)速率： 83MHz
訪問時間： 12ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
8
COMMERCIALTEMPERATURERANGE
IDT723624/723634/723644 CMOS SyncBiFIFO WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
—
83
—
66.7
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
12
—
15
—
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
5
—
6
—
ns
tCLKL
Pulse Duration, CLKA and CLKB LOW
5
—
6
—
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and B0-B35 before CLKB↑
3—
4
—
ns
tENS1
Setup Time,
CSA and W/RA before CLKA
↑; CSB and W/RB before CLKB↑
4
—
4.5
—
ns
tENS2
Setup Time ENA and MBA before CLKA
↑; ENB and MBB before CLKB↑
3
—
4.5
—
ns
tRSTS
Setup Time,
MRS1, MRS2, PRS1, or PRS2 LOW before CLKA
↑ or CLKB↑(2)
5—
5
—
ns
tFSS
Setup Time, FS0 and FS1 before
MRS1 and MRS2 HIGH
7.5
—
7.5
—
ns
tBES
Setup Time, BE/
FWFT before MRS1 and MRS2 HIGH
7.5
—
7.5
—
ns
tSPMS
Setup Time,
SPM before MRS1 and MRS2 HIGH
7.5
—
7.5
—
ns
tSDS
Setup Time, FS0/SD before CLKA
↑
3—
4
—
ns
tSENS
Setup Time, FS1/
SEN before CLKA
↑
3—
4
—
ns
tFWS
Setup Time, BE/
FWFT before CLKA
↑
0—
0
—
ns
tDH
Hold Time, A0-A35 after CLKA
↑ and B0-B35 after CLKB↑
0.5
—
1
—
ns
tENH
Hold Time,
CSA, W/RA, ENA, and MBA after CLKA
↑; CSB, W/RB, ENB, and MBB
0.5
—
1
—
ns
afterCLKB
↑
tRSTH
Hold Time,
MRS1, MRS2, PRS1 or PRS2 LOW after CLKA
↑ or CLKB↑(2)
4—
4
—
ns
tFSH
Hold Time, FS0 and FS1 after
MRS1 and MRS2 HIGH
2
—
2
—
ns
tBEH
Hold Time, BE/
FWFT after MRS1 and MRS2 HIGH
2
—
2
—
ns
tSPMH
Hold Time,
SPM after MRS1 and MRS2 HIGH
2
—
2
—
ns
tSDH
Hold Time, FS0/SD after CLKA
↑
0.5
—
1
—
ns
tSENH
Hold Time, FS1/
SEN HIGH after CLKA
↑
0.5
—
1
—
ns
tSPH
Hold Time, FS1/
SEN HIGH after MRS1 and MRS2 HIGH
2
—
2
—
ns
tSKEW1(3)
Skew Time between CLKA
↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA, and FFB/IRB
5
—
7.5
—
ns
tSKEW2(3,4)
Skew Time between CLKA
↑ and CLKB↑ for AEA, AEB, AFA, and AFB
12
—
12
—
ns
NOTES:
1. Industrial temperature range is available by special order.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
(Commercial: VCC = 5V ± 10%, TA = 0
°C to +70°C)
Commercial
IDT723624L12 IDT723624L15
IDT723634L12 IDT723634L15
IDT723644L12 IDT723644L15
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723624L12PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 128QFP
IDT723624L15PF 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723624L15PF8 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723624L15PFG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 128TQFP
IDT723624L15PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 128TQFP
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