![](http://datasheet.mmic.net.cn/IDT--Integrated-Device-Technology-Inc/IDT72291L20TFI_datasheet_105022/IDT72291L20TFI_18.png)
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
18
Figure
9.
Write
Timing
(First
Word
Fall
Through
Mode)
NOTES:
1.
tSKEW3
is
the
minimum
time
between
a
rising
WCLK
edge
and
a
rising
RCLK
edge
to
guarantee
that
OR
will
go
LOW
after
two
RCLK
cycles
plus
t
REF
.If
the
time
between
the
rising
edge
of
WCLK
and
the
rising
edge
of
RCLK
is
less
than
t
SKEW3
,then
OR
assertion
may
be
delayed
one
extra
RCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
WCLK
edge
and
a
rising
RCLK
edge
to
guarantee
that
PAE
will
go
HIGH
after
one
RCLK
cycle
plus
t
PAE
.If
the
time
between
the
rising
edge
of
WCLK
and
the
rising
edge
of
RCLK
is
less
than
t
SKEW2
,then
the
PAE
deassertion
may
be
delayed
one
extra
RCLK
cycle.
3.
LD
=
HIGH,
OE
=
LOW.
4.
n=
PAE
offset,
m
=
PAF
offset
and
D
=
maximum
FIFO
depth.
5.
D
=
65,537
for
the
IDT72281
and
131,073
for
the
IDT72291.
W
1
W
2
W
4
W
[n
+2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D
0
-
D
8
RCLK
tDH
tDS
tSKEW3
(1)
REN
Q
0
-Q
8
PAF
HF
PAE
IR
tDS
tSKEW2
tA
tREF
OR
tHF
tPAF
tWFF
W
[D-m+2]
W
1
tENH
4675
drw
12
DATA
IN
OUTPUT
REGISTER
(2)
W
3
1
2
3
1
D-1
]
[
W
D-1
]
[
W
D-1
]
[
W
1
2
tPAE