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參數(shù)資料
| 型號： | IDT7005L55G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | Single, Ultra Low Cost, RRIO CMOS Amplifier; Package: SOT-23; No of Pins: 5; Container: Tape & Reel |
| 中文描述： | 8K X 8 DUAL-PORT SRAM, 55 ns, CPGA68 |
| 封裝： | 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 189K |
| 代理商： | IDT7005L55G |
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
17
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
The
BUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
the other side is completed. If a write operation has been attempted from
thesidethatreceivesa
BUSYindication,thewritesignalisgatedinternally
to prevent the write from proceeding.
The use of
BUSYlogicisnotrequiredordesirableforallapplications.
In some cases it may be useful to logically OR the
BUSYoutputstogether
and use any
BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of
BUSYlogicis
not desirable, the
BUSYlogiccanbedisabledbyplacingthepartinslave
mode with the M/
Spin.OnceinslavemodetheBUSYpinoperatessolely
as a write inhibit input pin. Normal operation can be programmed by tying
the
BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the
BUSY pin for that port LOW.
The
BUSYoutputs on the IDT 7005 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the
BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7005 RAM array in width while using
BUSY
logic, one master part is used to decide which side of the RAM array will
receive a
BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSYsignalasawriteinhibitsignal.ThusontheIDT7005RAMtheBUSY
pinisanoutputifthepartisusedasamaster(M/
Spin=VIH),andtheBUSY
pin is an input if the part used as a slave (M/
S pin = VIL) as shown in
Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decision could result with one master indicating
BUSY ononesideofthe
array and another master indicating
BUSYononeothersideofthearray.
This would inhibit the write operations from one port for part of a word and
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
The
BUSY arbitration on a master is based on the chip enable and
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a
BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/
W signal.Failuretoobserve
thistimingcanresultinaglitchedinternalwriteinhibitsignalandcorrupted
data in the slave.
Semaphores
TheIDT7005isanextremelyfastDual-Port8Kx8CMOSStaticRAM
withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situations and may be used by the system program to avoid any conflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
an automatic power-down feature controlled by
CE,theDual-PortRAM
enable, and
SEM,thesemaphoreenable.TheCE and SEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where
CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT7005containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
aperformanceincreaseofferedbytheIDT7005'shardwaresemaphores,
which provide a lockout mechanism without requiring complex program-
ming.
Software handshaking between processors offers the maximum in
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
2738 drw 19
MASTER
Dual Port
RAM
BUSY (R)
CE
MASTER
Dual Port
RAM
BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (R)
CE
BUSY (L)
BUSY (R)
D
E
C
O
D
E
R
BUSY (L)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7005L55GB | Single, Ultra Low Cost, RRIO CMOS Amplifier |
| IDT7005L55J | Dual, Ultra Low Cost, RRIO CMOS Amplifier; Package: MSOP; No of Pins: 8; Container: Tape & Reel |
| IDT7005L55PF | Dual, Ultra Low Cost, RRIO CMOS Amplifier |
| IDT7005L55PFB | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005S | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7005L55GB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 55NS 68PGA |
| IDT7005L55J | 功能描述:IC SRAM 64KBIT 55NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7005L55J8 | 功能描述:IC SRAM 64KBIT 55NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7005L55JB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005L55JI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 55NS 68PLCC |
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