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參數(shù)資料
| 型號： | IDT5V19EE604NDGI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/29頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 200MHZ 28VFQFPN |
| 特色產(chǎn)品： | VersaClock III Timing Devices |
| 標準包裝： | 2,500 |
| 系列： | VersaClock™ III |
| 類型： | 時鐘發(fā)生器，多路復用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:6 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-VFQFPN（4x4） |
| 包裝： | 帶卷 (TR) |
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IDT5V19EE604
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
13
IDT5V19EE604
REV M 092412
Programming the Device
I2C may be used to program the IDT5V19EE604.
– Device (slave) address = 7'b1101010
I2C Programming
The IDT5V19EE604 is programmed through an I2C-Bus
serial interface, and is an I2C slave device. The read and
write transfer formats are supported. The first byte of data
after a write frame to the correct slave address is interpreted
as the register address; this address auto-increments after
each byte written or read.
The frame formats are shown in the following illustration.
Framing
First Byte Transmitted on I2C Bus
External I2C Interface Condition
Progwrite
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
1
0
1
0
1
0
1
MSB
LSB
R/W
ACK from Slave
R/W
0 – Slave will be written by master
1 – Slave will be read by master
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a “1” bit.
7-bit slave address
KEY:
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a separate START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDAT LOW)
NACK – Not Acknowledge (SDAT HIGH)
SR – Repeated Start Condition
S – START Condition
P – STOP Condition
SAddress
R/W
ACK
Command Code
ACK
Register
ACK
Data
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx00
1-bit
8-bits
1-bit
8-bits
1-bit
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V19EE901NLGI | 功能描述:IC PLL CLK GEN 200MHZ 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDT5V19EE901NLGI8 | 功能描述:IC PLL CLK GEN 200MHZ 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V19EE901PGGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR |
| IDT5V19EE901PGGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN VCXO PROGR 28TSSOP |
| IDT5V19EE902-EVB | 制造商:Integrated Device Technology Inc 功能描述:EVAL BOARD FOR IDT 5V19EE902 |
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