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參數(shù)資料
| 型號： | ID82C85 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Static Clock Controller/Generator |
| 中文描述： | 24 MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 363K |
| 代理商： | ID82C85 |
301
until the oscillator signal amplitude reaches the X1 Schmitt
trigger input threshold voltage and 8192 cycles of the crystal
oscillator output are counted by an internal counter. After
this count is complete, the stopped outputs (CLK, CLK50,
PCLK, and OSC) start cleanly with the proper phase rela-
tionships.
Typically, any input signal which meets the START input tim-
ing requirements can be used to start the 82C85. In many
cases, this would be the INT output from an 82C59A CMOS
Priority Interrupt Controller (See Figure 1). This output,
which is active high, can be connected to both the 82C85
START pin and to the appropriate interrupt request input on
the microprocessor.
When the INT output becomes active, the oscillator/clock cir-
cuit on the 82C85 will restart. Upon completion of the appro-
priate restart sequence, the CLK signal to the CPU will
become active. The CPU can then respond to the still pend-
ing interrupt request.
If the 82C59A/82C85 restart combination is used in conjunc-
tion with an 82C55A STOP control, the 82C55A must be ini-
tialized prior to the 82C59A after reset. The 82C59A
interrupt output is driven high at reset, causing the 82C85 to
remain in the START mode regardless of the state of the
S2/STOP input. This will avoid stopping the 82C85 due to
negative transitions on the S2/STOP input which may occur
during a mode change on the 82C55A or during the opera-
tion of any peripheral I/O device prior to initialization.
Another method of insuring proper operation of the START
function upon reset or system initialization is to bias the
S2/STOP input low with an external pull-down resistor. The
S2/STOP input will remain low until driven high by the
82C55A port pin or by external logic. This insures that the
82C85 STOP command (HHH prior to LHH requirement on
the status inputs) will not be satisfied. To minimize power
dissipation in this case (using a pulldown resistor), the
S2/STOP input should be normally LOW and pulsed HIGH
to develop the necessary HHH-to-LHH STOP sequence. In
this manner, the output driving the S2/STOP input will be
normally LOW and will not be driving to the opposite state of
the pull-down resistor.
Fast Mode
The most common operating mode for a system is the FAST
mode. In this mode, the 82C85 operates at the maximum fre-
quency determined by the main oscillator or EFI frequency.
82C59A
82C85
START
CLK
S0
S1
S2/STOP
SLO/FST
80C86/88
INTR
CLK
PA0 PA1
82C55A
INT
V
CC
FIGURE 1. CMOS PERIPHERAL CONTROL OF 82C85 STOP,
START AND SLOW/FAST OPERATIONS
TABLE 2. TYPICAL SYSTEM POWER SUPPLY CURRENT FOR STATIC CMOS OPERATING MODES
FAST
SLOW
STOP-CLOCK
STOP-OSC
CPU Frequency
5MHz
20 KHz
DC
DC
XTAL Frequency
15MHz
15MHz
15MHz
DC
ICC
82C85
24.7mA
16.9mA
14.1mA
24.4mA
80C88
23.8mA
173.0mA
106.6mA
106.6mA
82C82
1.7mA
6.5mA
1.0mA
1.0mA
82C86
1.4mA
14.0mA
1.0mA
1.0mA
82C88
3.5mA
14.3mA
3.8mA
3.8mA
82C52
151.2mA
72.0mA
1.0mA
1.0mA
82C54
943.0mA
915.0mA
3.5mA
1.0mA
82C55A
3.2mA
1.2mA
1.0mA
1.0mA
82C59A
580.0mA
520.0mA
1.0mA
1.0mA
74HCXX + other
2.9mA
10.0mA
90.0mA
90.0mA
HM-6516
820.0mA
32.0mA
1.9mA
1.9mA
HM-6616
6.3mA
52.5mA
12.0mA
12.0mA
Total
66.8mA
18.9mA
14.3mA
244.7mA
All measurements taken at room temperature, V
CC
= +5.0V. Power supply current levels will be dependent upon system configuration and
frequency of operation.
82C85
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相關代理商/技術參數(shù) |
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| ID82C85/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| ID82C86H | 功能描述:總線收發(fā)器 20 CDIP -40+85C 5 0V 32NS OCTL BUS TRANSC RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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| ID82C87H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Inverting Bus Transceiver |
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