參數(shù)資料
型號: ID82C284-10
廠商: INTERSIL CORP
元件分類: XO, clock
英文描述: Clock Generator and Ready Interface for 80C286 Processors
中文描述: 10 MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP18
封裝: CERDIP-18
文件頁數(shù): 10/11頁
文件大小: 72K
代理商: ID82C284-10
10
Waveforms
NOTE:
1. The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown.
FIGURE 9. CLK AS A FUNCTION OF EFI
NOTE:
1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
FIGURE 10. RESET AND READY TIMING AS A FUNCTION OF RES WITH S1, S0, ARDY + ARDYEN, AND SRDY + SRDYEN HIGH
NOTES:
1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
2. If SRDY + SRDYEN or ARDYEN are active before and/or during the first bus cycle after RESET, READY may not be deasserted until the
falling edge of
φ
2 of T
S
.
FIGURE 11. READY AND PCLK TIMING WITH RES HIGH
EFI
CLK
t
15B
t
19
t
1
t
2
t
17
t
20
t
18
t
16
t
15A
t
16
t
13
t
14
t
14
t
13
t
24
t
22
t
24
t
21
SEE
NOTE
DEPENDS ON STATE
OF PREVIOUS RES
CLK
RES
RESET
READY
t
6
t
5A
t
6
t
5B
t
23
t
23
t
21
t
11
t
21
t
12
t
9
t
11
t
10
t
25
t
26
t
12
t
22
T
S
T
C
φ
1
φ
2
φ
1
φ
2
CLK
S1
S0
PCLK
SRDY + SRDYEN
ARDY + ARDYEN
READY
NOTE 2
NOTE 1
UNDEFINED
FIRST BUS CYCLE
IF THIS IS
82C284
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