參數(shù)資料
型號： ID80C86-2
廠商： HARRIS SEMICONDUCTOR
元件分類： 微控制器/微處理器
英文描述： CMOS 16-Bit Microprocessor
中文描述： 16-BIT, 8 MHz, MICROPROCESSOR, CDIP40
文件頁數(shù)： 6/35頁
文件大?。?/td> 339K
代理商： ID80C86-2
3-146
DT/R
27
O
DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus
transceiver. It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,
R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DEN
26
O
DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system which
uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cy-
cles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a
write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high im-
pedance logic one during local bus “hold acknowledge”.
HOLD
HLDA
31, 30
I
O
HOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged,
HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge”
(HLDA) in the middle of a T4 or TI clock cycle. Simultaneously with the issuance of HLDA, the
processor will float the local bus and control lines. After HOLD is detected as being LOW, the
processor will lower HLDA, and when the processor needs to run another cycle, it will again drive
the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system
cannot otherwise guarantee the setup time.
Maximum Mode System
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are
unique to maximum mode are described below.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
S0
S1
S2
26
27
28
O
O
O
STATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3
or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate
all memory and I/O access control signals. Any change by S2, S1 or S0 during T4 is used to
indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to
indicate the end of a bus cycle.
These signals are held at a high impedance logic one state during “grant sequence”.
Minimum Mode System
(Continued)
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V
CC
). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
S2
S1
S0
CHARACTERISTICS
0
0
0
Interrupt Acknowledge
0
0
1
Read I/O Port
0
1
0
Write I/O Port
0
1
1
Halt
1
0
0
Code Access
1
0
1
Read Memory
1
1
0
Write Memory
1
1
1
Passive
80C86
相關PDF資料
PDF描述
ID80C88 CMOS 8/16-Bit Microprocessor
ID80C88-2 CMOS 8/16-Bit Microprocessor
ID82C284-10 Clock Generator and Ready Interface for 80C286 Processors
ID82C284-12 Clock Generator and Ready Interface for 80C286 Processors
ID82C284 Clock Generator and Ready Interface for 80C286 Processors
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