IDTTM/ICSTM Four Output Differential Buff" />
參數(shù)資料
型號(hào): ICS9DS400AGLFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 7/19頁(yè)
文件大?。?/td> 0K
描述: IC CLK SPREAD INJECTION 28TSSOP
標(biāo)準(zhǔn)包裝: 1,000
類型: *
PLL: 帶旁路
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無(wú)/是
除法器/乘法器: 無(wú)/無(wú)
電源電壓: 3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
15
Advance Information
Asserting DIF_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the DIF_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
DIF_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
DIF_STOP# - Assertion
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the DIF_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
DIF_STOP# - De-assertion (transition from '0' to '1')
The DIF_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on DIF_IN for this input to work properly. The DIF_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
DIF_STOP#
DIF_STOP_1 (DIF_Stop = Driven, PD = Driven)
DIF_STOP_2 (DIF_Stop =Tristate, PD = Driven)
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
DIF
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
DIF
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