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參數(shù)資料
| 型號： | ICS9250YF-33-T |
| 元件分類： | XO, clock |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, SSOP-56 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 178K |
| 代理商： | ICS9250YF-33-T |
Integrated
Circuit
Systems, Inc.
ICS9250-33
Third party brands and names are the property of their respective owners.
9250-33 Rev - 5/14/01
Advance Information
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
Pin Configuration
56-Pin 300mil SSOP & TSSOP
* This input has a 120K internal pull down to GND.
Recommended Application:
Output Features:
4 Differential CPU Clock Pairs @ 3.3V
2 - 3V MREF clocks for memory reference seeds,
(separate single ended but 180 degrees out of phase)
4 - 66MHz reference output
10 - 3V 33MHz PCI clocks
2 - 48MHz clocks
2 - 14.318 reference output
Features:
Up to 156MHz frequency support
Support power management: Power Down Mode
Supports Spread Spectrum modulation: 0 to -0.5% down
spread.
Uses external 14.318MHz crystal
Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum, limited
frequency select, selective clock enable.
External resistor for current reference
FS pins for frequency select
Key Specifications:
3V66 Output jitter <300ps
CPU Output Jitter <200ps
MREF Output jitter <250ps
Frequency Generator for Celeron/PIII
GND
REF
VDDREF
X1
X2
GNDREF
PCICLK0
PCICLK1
VDDPCI
PCICLK2
PCICLK3
GNDPCI
PCICLK4
PCICLK5
VDDPCI
PCICLK6
*FS2/PCICLK7
GNDPCI
PCICLK8
PCICLK9
VDDPCI
SEL100/133
GND48
48MHz
48MHz
VDD48
PD#
MULTSEL0/
MULTSEL1/REF
FS0/
FS1/
VDDMREF
3VMREF
3VMREF_B
GNDMREF
SPREAD#
CPUCLKT3
CPUCLKC3
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
I REF
VDDA
GNDA
VDD3V66
3V66-3
3V66-2
GND3V66
GND3V66
3V66-1
3V66-0
VDD3V66
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Functionality
PLL2
PLL1
Spread
Spectrum
48MHz
3VMREF
PCICLK [0:9]
3VMREF_B
3V66 [0:3]
4
10
2
2
X1
X2
XTAL
OSC
CPU
DIVDER
3VMREF
DIVDER
PCI
DIVDER
3V66
DIVDER
PD#
SPREAD#
MULTSEL[0:1]
SEL100/133
]
FS[2:0
Control
Logic
Config.
Reg.
REF
4
4
CPUCLKT [0:3]
CPUCLKC [0:3]
/
3
0
1
L
1
E
S
0
0
0
S
F
1
S
F
n
o
n
u
F
0
0
z
H
M
0
0
1
e
v
A
0
0
1
z
H
M
5
0
1
0
1
0
z
H
M
0
0
2
0
1
1
s
p
o
l
e
T
1
0
0
z
H
M
3
3
1
e
v
A
1
0
1
z
H
M
6
2
1
1
1
0
z
H
M
0
0
2
1
1
1
e
d
o
M
t
T
* FS2 = 1: Margin testing mode
Block Diagram
Power Groups
VDDREF, GNDREF= REF, X1, X2
VDDPCI, GNDPCI = PCICLK
VDD48, GND48 = 48MHz, PLL2
VDD3V66, GND3V66=3V66
VDDCPU, GNDCPU = CPUCLK
VDDMREF, GNDMREF=3VMREF, 3VMREF_B
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
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