參數(shù)資料
型號(hào): ICS9179F-06
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: PLL BASED CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: SSOP-48
文件頁(yè)數(shù): 6/8頁(yè)
文件大小: 496K
代理商: ICS9179F-06
6
ICS9179-06
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Frequency
FO3
33
133
MHz
Output Impedance
RDSP3
VO = VDD*(0.5)
10
24
Ohm
Output Impedance
RDSN3
VO = VDD*(0.5)
10
24
Ohm
Output High Voltage
VOH3
IOH = -30 mA
2.6
V
Output Low Voltage
VOL3
IOL = 23 mA
0.4
V
Output High Current
IOH3
VOH = 2.0 V
-54
mA
Output Low Current
IOL3
VOL = 0.8 V
40
mA
Rise Time
Tr3
VOL = 0.4 V, VOH = 2.4 V
1.33
nS
Fall Time
Tf3
VOH = 2.4 V, VOL = 0.4 V
1.33
nS
Duty Cycle
Dt3
VT = 1.5 V
45
55
%
Output to Output
Skew Window
Tsk3
VT = 1.5 V
250
pS
Tskd1
VT = 1.5 V default Zero delay I
2C
B0 bits 0, 1 = 00
-250
0
250
pS
IN to FB_IN Skew
1, 2
Tskd2
VT = 1.5 V bits 0, 1 = 10
-2.2
-2.7
-3.2
nS
Tskd3
VT = 1.5 V bits 0, 1 = 01
+1.5
+2.0
+2.5
nS
Tskd4
VT = 1.5 V bits 0, 1 = 11
-0.2
-0.7
-1.2
nS
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
Notes:
1. Guarenteed by design, not 100% tested in production
2. Delay elements FBIN and clock INPUT path are selected by I2C BYTE2; bit 0 = clock input control, bit 1 = Clock INPUT
Control. (Default is 0). A 0 = No delay in path, 1 = Delay element selected.
Note: PWD = Power-Up Default
Input Pulse
N
I
MP
Y
TX
A
MS
T
I
N
U
e
s
l
u
P
t
u
p
n
I
e
m
i
T
w
o
L
T
w
o
L
-
m
i
w
o
L
_
e
s
l
u
p
V
V
8
.
00
.
1s
n
e
s
l
u
P
t
u
p
n
I
e
m
i
T
h
g
i
H
T
h
g
i
H
-
m
i
h
g
i
H
_
e
s
l
u
p
V
V
0
.
25
.
1s
n
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