參數(shù)資料
型號(hào)： ICS9169CJ-271LF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO32
封裝： SOJ-32
文件頁(yè)數(shù)： 7/8頁(yè)
文件大?。?/td> 322K
代理商： ICS9169CJ-271LF
7
ICS9169C-271
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7 V, TA = 0 –70° C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time
1
Tr1
20pF load, 0.8 to 2.0V
CPU & BUS
-
0.9
1.5
ns
Fall Time
1
Tf1
20pF load, 2.0 to 0.8V
CPU & BUS
-
0.8
1.4
ns
Rise Time
1
Tr2
20pF load, 20% to 80%
CPU & BUS
-
1.5
2.5
ns
Fall Time
1
Tf2
20pF load, 80% to 20%
CPU & BUS
-
1.4
2.4
ns
Duty Cycle1
Dt
20pF load @ VOUT=1.4V
455060
%
Jitter, One Sigma
1
Tj1s1
CPU & BUS Clocks; Load=20pF,
BSEL=1
-
50
150
ps
Jitter, Absolute
1
Tjab1
CPU & BUS Clocks; Load=20pF,
BSEL=1
-250
-
250
ps
Jitter, One Sigma
1
Tj1s2
REF & Fixed CLKs; Load=20pF
-
1
3
%
Jitter, Absolute1
Tjab2
REF & Fixed CLKs; Load=20pF
-5
2
5
%
Input Frequency
1
Fi
12.0
14.318
16.0
MHz
Logic Input Capacitance1
CIN
Logic input pins
-
5
-
pF
Crystal Oscillator Capacitance
1
CINX
X1, X2 pins
-
18
-
pF
Power-on Time1
ton
From VDD=1.6V to 1st crossing of
66.6 MHz VDD supply ramp < 40ms
-
2.5
4.5
ms
Clock Skew
1
Tsk1
CPU to CPU; Load=20pF; @1.4V
-
150
250
ps
Clock Skew
1
Tsk2
BUS to BUS; Load=20pF; @1.4V
-
160
500
ps
Clock Skew1
Tsk3
CPU to BUS; Load=20pF; @1.4V
(CPU is early)
1
2.2
4
ns
Clock Skew1
Tsk4
CPU (@3.3V) to CPU (@2.5V)
(2.5V CPU is late)
0.5
1
ns
相關(guān)PDF資料
PDF描述
ICS9169CJ-271 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO32
ICS9169CM-271LF 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO32
ICS9169M-01 66.5 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
ICS9169F-01 66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
ICS9169M-01LF 66.5 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
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