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參數(shù)資料
| 型號： | ICS9169CF-46LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO34 |
| 封裝： | SSOP-34 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 355K |
| 代理商： | ICS9169CF-46LF |
3
ICS9169C-46
Technical Pin Function Descriptions
VDD
This is the power supply to the internal logic of the device as
well as the following clock output buffers:
This pin may be operated at any voltage between 3.0 to 3.7
volts. Clocks from the listed buffers that it supplies will have
a voltage swing from ground to this level. For the actual
guaranteed high and low voltage levels of these clocks,
please consult the AC parameter table in this data sheet.
GND(VSS)
This is the power supply ground return pin for the internal
logic of the device as well as the following clock output
buffers:
A. REF clock output buffers
B. CPU clock output buffers
X1
This pin serves one of two functions. When the device is
used with a crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal.
When the device is driven by an external clock signal, X1
is the device input pin for that reference clock. This pin
also implements an internal crystal loading capacitor that
is connected to ground. See the data tables for the value of
the capacitor.
X2
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2
is an output signal that drives (or excites) the discrete
crystal. This pin also implements an internal crystal loading
capacitor that is connected to ground. See the data tables
for the value of the capacitor.
CPUCLK (0:15)
This pin is the clock output that drives processor and other
CPU related circuitry that require clocks which are in tight
skew tolerance with the CPU clock. See the Functionality
table at the beginning of this data sheet for a list of the
specific frequencies that this clock operates at and the
selection codes that are necessary to produce these
frequencies.
PCICLK
Clock output driver.
FS0, FS1
These pins control the frequency of the clocks at the CPU,
and PCI. See the Funtionality table at the beginning of this
data sheet for a list of the specific frequencies that this clock
operates at and the selection codes that are necessary to
produce these frequencies. If a "1" value is desired for a
specific frequency selection bit,a 10K ohm restor must be
connected from the appropriate FS pin to the VDD supply. If
a "0" value is desired, then the 10K resistor must be connected
to ground.
48MHz
This is a fixed frequency clock that is typicaly used to drive
USB peripheral device needs.
24MHz
This is a fixed frequency clock that is typicaly used to drive
super I/O peripheral device needs.
REF0
This is a fixed frequency clock that runs at the same frequency
as the input freerence clock (typically 14.31818 MHz) is
and typically used to driveVideo and ISABUS requirements.
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| ICS9169CF-46 | 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO34 |
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