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參數(shù)資料
| 型號(hào)： | ICS9120-56 |
| 英文描述： | Frequency Timing Generator for EtherNet & Hard Drives |
| 中文描述： | 以太網(wǎng)時(shí)鐘頻率發(fā)生器 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 106K |
| 代理商： | ICS9120-56 |
2
ICS9120-08
ICS9120-09
Pin Configuration
Pin Descriptions for ICS9120-08
Functionality
PIN NUMBER
1
2
3
4
5
6
7
8
Pin Descriptions for ICS9120-09
PIN NAME
X1
V
DD
GND
CLK3
CLK1
CLK2
REF
X2
TYPE
Input
Power
Power
Output
Output
Output
Output
Output
DESCRIPTION
Crystal or external clock source. Has feedback bias for crystal.
Power supply input.
Ground return for Pin 2.
16.934 MHz target output clock for stereo codec.
24.576 MHz target output clock for stereo codec.
33.868 MHz target output clock for OPL4.
14.318 MHz reference clock buffered output.
Crystal output drive.
PIN NUMBER
1
2
3
4
5
6
7
8
PIN NAME
X1
VDD
GND
CLK3
CLK1
CLK2
REF
PD#
TYPE
Input
Power
Power
Output
Output
Output
Output
Input
DESCRIPTION
External clock source.
Power supply input.
Ground return for Pin 2.
16.934 MHz target output clock for stereo codec.
24.576 MHz target output clock for stereo codec.
33.868 MHz target output clock for OPL4.
14.318 MHz reference clock buffered output.
Power-down input powers down entire device when low; has pull-up.
Note:
(Pin 8) is internally pulled-up to V
DD
and, therefore, may
be left disconnected or driven by open collector logic.
8-Pin SOIC
8-Pin SOIC
X1, X2
(MHz)
-
14.318
-
(-09 only)
PD#
0
1
33.9
(MHz)
Low
33.868
16.9
(MHz)
Low
16.934
24.6
(MHz)
Low
24.576
14.3
(MHz)
Low
14.318
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| ICS9120M-08 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator for Multimedia Audio Synthesis |
| ICS9120M-09 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator for Multimedia Audio Synthesis |
| ICS9120M-11 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator for Multimedia Audio Synthesis |
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