參數(shù)資料
型號: ICS9112M-18T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 91 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 3/4頁
文件大?。?/td> 52K
代理商: ICS9112M-18T
ICS9112-18
Zero Delay, Low Skew Buffer
ADVANCE INFORMATION
MDS9112-18B
3
Revision 12038
Printed 12/11/98
Integrated Circuit Systems 525 Race Street San Jose CA 95126 (408)295-9800tel(408)295-9818fax
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
-0.5
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Electrostatic Discharge
MIL-STD-883
2000
V
Ambient Operating Temperature
0
70
C
Soldering Temperature
Max of 10 seconds
260
C
Junction temperature
150
C
Storage temperature
-65
150
C
DC CHARACTERISTICS
Operating Voltage, VDD
3.00
5.50
V
Input High Voltage, VIH, CLKIN pin only
VDD/2+1
VDD/2
V
Input Low Voltage, VIL, CLKIN pin only
VDD/2
VDD/2-1
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load
TBD
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance
S2, S1, FBIN
7
pF
AC CHARACTERISTICS
Input Clock Frequency
TBD
135
MHz
Output Clock Frequency
TBD
135
MHz
Output Clock Rise Time, CL=30pF
0.8 to 2.0V
1.5
ns
Output Clock Fall Time, CL=30pF
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle, VDD=3.3V
At 1.4V
40
50
60
%
Device to Device Skew, equally loaded
rising edges at VDD/2
700
ps
Output to Output Skew, equally loaded
rising edges at VDD/2
250
ps
Maximum Absolute Jitter
TBD
ps
Cycle to Cycle Jitter, 30pF loads
66.67 MHz outputs
500
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
相關(guān)PDF資料
PDF描述
ICS9112YG-16-T PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS9112YG-27LF-T LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS9112YG-27LF-T LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS9112YM-17-T PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS9112YM-17-T PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS9112M-22 功能描述:IC CLK BUFFER DVR 133MHZ 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器,驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器(分配) 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL,LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN(5x5) 包裝:管件
ICS9112M-31 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator for Fibre Channel Systems
ICS9112M-32 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator for Fibre Channel Systems
ICS9112M-33 功能描述:IC CLOCK DRIVER LO JITTER 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP (0.240",6.10mm 寬) 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
ICS9112M-33T 功能描述:IC CLOCK DRIVER LO JITTER 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP (0.240",6.10mm 寬) 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件