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參數(shù)資料
| 型號： | ICS9112BM-18LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 74K |
| 代理商： | ICS9112BM-18LFT |
ICS9112-18
MDS 9112-18 G
1
Revision 121302
In tegr ated C i r cu i t S y st ems q 5 25 Ra ce Str eet, San Jose, C A 95 126 q tel ( 408) 2 95-9 800 q
w w w.ic s t .c o m
ZERO DELAY, LOW SKEW BUFFER
Description
The ICS9112-18 is a low jitter, low skew, high
performance Phase Lock Loop (PLL) based zero delay
buffer for high speed applications. Based on ICS’
proprietary low jitter PLL techniques, the device
provides eight low skew outputs at speeds up to 160
MHz at 3.3V. The ICS9112-18 includes a bank of four
outputs running at 1/2X. In the zero delay mode, the
rising edge of the input clock is aligned with the rising
edges of all eight outputs. Compared to competitive
CMOS devices, the ICS9112-18 has the lowest jitter.
ICS manufactures the largest variety of clock
generators and buffers and is the largest clock supplier
in the world.
Features
Packaged in 16 pin SOIC
Zero input-output delay
Four 1X outputs plus four 1/2X outputs
Output to output skew is less than 250 ps
Output clocks up to 160 MHz at 3.3V
Ability to generate 2X the input
Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3V
Spread SmartTM technology works with spread
spectrum clock generators
Advanced, low power, sub micron CMOS process
Operating voltage of 3.3V or 5V
Block Diagram
CLKA4
CLKB1
CLKA3
CLKB2
CLKB3
CLKA2
CLKA1
CLKB4
Control
Logic
S1, S0
2
PLL
FBIN
CLKIN
/2
VDD
2
GND
2
相關PDF資料 |
PDF描述 |
|---|---|
| ICS9112CM-18 | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS9112CM-18LFT | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS9112CM-18 | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS9112M-16LF | 91 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112M-16 | 91 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9112BM-18T | 制造商:ICS 制造商全稱:ICS 功能描述:Zero Delay, Low Skew Buffer |
| ICS9112CM18 | 制造商:ICS 功能描述: |
| ICS9112M-06 | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS9112M-07 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew Output Buffer |
| ICS9112M-22 | 功能描述:IC CLK BUFFER DVR 133MHZ 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:- 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:管件 |
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