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參數(shù)資料
| 型號： | ICS874005AGLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI EXPRSS/JITT ATTEN 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™, PCI Express® (PCIe) |
| 類型： | 扇出緩沖器（分配），漂移衰減器 |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 輸入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 160MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 874005AGLFT |
ICS874005AG REVISION B JANUARY 12, 2012
9
2012 Integrated Device Technology, Inc.
ICS874005 Data Sheet
PCI EXPRESS JITTER ATTENUATOR
SCHEMATIC EXAMPLE
FIGURE 5. ICS874005 SCHEMATIC EXAMPLE
D
Figure 5 is an ICS874005 application example schematic.
The schematic focuses on functional connections and is not
configuration specific. Refer to the pin description and
functional tables in the datasheet to ensure that the logic
control inputs are properly set. The input is provided by 3.3V
LVPECL driver with a Y-termination for simplicity, ease of
layout and better control of the termination power over
device variations. As with any high speed analog circuitry,
the power supply pins are vulnerable to random noise. To
achieve optimum jitter performance, power supply isolation
is required. The ICS874005 provides separate VDD and
VDDO power supplies to isolate any high switching noise
from coupling into the internal PLL. In order to achieve the
best possible filtering, it is recommended that the place-
ment of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is
limited, the 0.1uF capacitor in each power pin filter should
be placed on the device side. The other components can be
on the opposite side of the PCB. Power supply filter recom-
mendations are a general guideline to be used for reducing
external noise from coupling into the devices. The VCC and
VCCO filters start to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as
switching power supplies frequencies, it is recommended
that component values be adjusted and if required, addi-
tional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding
bulk capacitance in the local area of all devices.
U1
nQB2
1
nQA1
2
QA1
3
VDD O
4
QA0
5
nQAO
6
MR
7
BW_SEL
8
VDD A
9
F_SELA
10
VDD
11
OEA
12
CLK
13
nC LK
14
GN D
15
GN D
16
OEB
17
F_SELB
18
nQ B0
19
QB0
20
nQ B1
21
QB1
22
VDD O
23
QB2
24
BLM18BB221SN4
FB2
1
2
C9
0.1uF
3.3V
C8
10uF
VDDO
C7
.1uf
VDD O
VDD
RU2
Not I nst all
RU1
1K
RD2
1K
RD1
Not Install
VCC
To Logic
Input
pins
Set Logic
Input to '0'
To Logic
Input
pins
Logic Control Input Examples
Set Logic
Input to '1'
R2
100
+
-
Zo = 50 Ohm
C2
10uF
C1
0.1uF
3.3V
BLM18BB221SN1
FB1
1
2
C3
10uF
R3
100
+
-
R1
10
C4
0.01u
Zo = 50 Ohm
QB1
nQB1
QA0
nQB2
nQA0
QB2
nQA1
CLK
nCLK
OEA
F_SELA
MR
BW_SEL
OEB
F_SELB
VD DO
C5
.1uf
C6
.1uf
LVPECL Driv er
Zo = 50 O hm
R6
50
R5
50
R4
50
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