1-TO-6, LVPECL-
參數(shù)資料
型號(hào): ICS87158AFLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/17頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 1-6 HCSL 48-SSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: HiPerClockS™
類型: 時(shí)鐘發(fā)生器
PLL:
輸入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: HCSL,LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:7
差分 - 輸入:輸出: 是/是
頻率 - 最大: 600MHz
除法器/乘法器: 是/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 帶卷 (TR)
其它名稱: 87158AFLFT
87158AG
www.idt.com
REV. C JULY 25, 2010
11
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS
÷1, ÷2, ÷4 CLOCK GENERATOR
Power and Ground
This section provides a layout guide related to power,
ground and placement of bypass capacitors for a high-
speed digital IC. This layout guide is a general recommen-
dation. The actual board design will depend on the compo-
nent types being used, the board density and cost con-
straints. The description assumes that the board has clean
power and ground planes. The principle is to minimize the
ESR between the clean power/ground plane and the IC
power/ground pin.
A low ESR bypass capacitor should be used on each power
pin. The value of bypass capacitors ranges from 0.01uF to
0.1uF. The bypass capacitors should be located as close
IC
C
VIA
GND Pin
Power
Pin
GND
Pads
POWER
Pads
FIGURE 4. RECOMMENDED LAYOUT OF BYPASS CAPACITOR PLACEMENT
to the power pin as possible. It is preferable to locate the
bypass capacitor on the same side as the IC. Figure 4
shows suggested capacitor placement. Placing the by-
pass capacitor on the same side as IC allows the capaci-
tor to have direct contact with the IC power pin. This can
avoid any vias between the bypass capacitor and the IC
power pins.
The vias should be place at the Power/Ground pads. There
should be minimum one via per pin. Increase the number
of vias from the Power/Ground pads to Power/Ground
planes can improve the conductivity.
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