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參數(shù)資料
| 型號： | ICS84330AV-02LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/19頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER 700MHZ 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | HiPerClockS™ |
| 類型： | 頻率合成器 |
| PLL： | 是 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 700MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.5x11.5） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 84330AV-02LFT |
84330AV-02
www.idt.com
REV. B JULY 25, 2010
2
ICS84330-02
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
divider. On the LOW-to-HIGH transition of the nP_LOAD input,
the data is latched and the M divider remains loaded until the
next LOW transition on nP_LOAD or until a serial event occurs.
The TEST output is Mode 000 (shift register out) when operat-
ing in the parallel input mode. The relationship between the VCO
frequency, the crystal frequency and the M divider is defined as
follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 125
≤ M ≤ 350. The frequency out is defined as
follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and
test bits T2:T0. The internal registers T2:T0 determine the state
of the TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
The ICS84330-02 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A quartz crystal is used as the input to the on-chip
oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84330-02 support two
input modes to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode the
nP_LOAD input is LOW. The data on inputs M0 through M8 and
N0 through N1 is passed directly to the M divider and N output
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
16
2M
fVCO = fxtal x
N
fout = fVCO =
16
2M
fxtal x
N
Time
SERIAL LOADING
PARALLEL LOADING
t
S
t
H
t
S
t
H
t
S
M, N
T2
T1
T0
TEST Output
0
Shift Register Out
0
1
High
0
1
0
PLL Reference Xtal ÷ 16
0
1
(VCO ÷ M) /2 (non 50% Duty Cycle M divider)
1
0
fOUT
LVCMOS Output Frequency < 200MHz
1
0
1
Low
1
0
(S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider)
1
fOUT ÷ 4
fOUT
fOUT
S_CLOCK ÷ N divider
fOUT
T2
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
NOTE: nP_LOAD is designed to eliminate runt pulses when changing M and N bits.
S_LOAD
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| ICS84330AV-02T | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330AY03 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330AY-03 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330AY-03LF | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330AY-03LFT | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
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