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參數(shù)資料
| 型號： | ICS8432BY-21T |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 111K |
| 代理商： | ICS8432BY-21T |
8432-21
www.icst.com/products/hiperclocks.html
APRIL 2, 2001
2
ADVANCE INFORMATION
Integrated
Circuit
Systems, Inc.
ICS8432-21
700/87.5MHZ, LOW PHASE NOISE
LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1.
The ICS8432-21 features a fully integrated PLL and therefore requires no external component for setting the loop bandwidth.
A parallel-resonant , fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the
phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over
a range of 250MHz to 700MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter divider force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to the LVPECL output buffer FOUT. The output of this divider is
scaled by a second divider prior to being sent to the LVPECL output buffer FOUT/P. These dividers provide a 50% output duty
cycle.
The programmable features of the ICS8432-21 support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel
mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0, N1, and P0 is passed directly to the
ripple counter and the output dividers. On the LOW-to-HIGH transition of the nP_LOAD input the data is latched and the ripple
counter and output dividers remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a
result the M, N, and P bits can be hardwired to set the ripple counter and output dividers to a specific default state that will
automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the loop divider is defined as follows:
The M count and the required values of M0 through M8 are shown in Table 4B, Programmable VCO Frequency Function.
Valid M values for which the PLL will achieve lock are defined as 10
≤ M ≤ 28. The frequency out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the ripple counter and output dividers
when S_LOAD transitions from LOW-to-HIGH. The ripple counter and output divider values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH data at the S_DATA input is passed directly to the ripple counter and output
dividers on each rising edge of S_CLOCK. The serial mode can be used to program the M, N, and P bits and test bits T1 and
T0. The internal registers T0 and T1 determine the state of the TEST output as follows:
fVCO = fxtal x M
T1
T0
TEST Output
0
LOW
0
1
S_Data
1
0
Output of M divider
1
CMOS Fout
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
T1
T0
P0
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N2
nP_LOAD
Time
N x P
FOUT/P =
fVCO
=
M __
fxtal x
N x P
N
FOUT =
fVCO
=
M __
fxtal x
N
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