參數(shù)資料
型號(hào)： ICS8431AM-01
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, OTHER CLOCK GENERATOR, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 2/7頁(yè)
文件大?。?/td> 96K
代理商： ICS8431AM-01
Integrated
Circuit
Systems, Inc.
8431-01
www.icst.com
SEPTEMBER 13, 2000
2
ICS8431-01
CLOCK SYNTHESIZER
PRELIMINARY
CONFIGURATION PROGRAMMING INTERFACE
Programming the Spread Spectrum Clocking (SSC) feature is accomplished by configuring the internal PUL register. The input to
this register is encoded by the SSC_CTL[1:0] pins which define all functional states after power is applied. Figure 1 shows the timing
relationship of the latched SSC_CTL[1:0] in relationship to the PLL power-on condition.
After power is applied, the control bits SSC_CTL0 and SSC_CTL1 are latched after approximately 100s. TPUL_SU is the time
during which the data on the control bits is required to be valid before being latched. TPUL_HD is the time after the data is latched that
the control bits are required to remain valid. The configuration latch can only be overwritten by removing the power and applying data
to the inputs that meet the setup and hold time requirment during power-on, as defined in Figure 1. Table 3, Input Function Table
defined the valid commands for SSC_CTL[1:0] lines.
FIGURE 1. POWER-UP CONFIGURATION TIMING
t = 100s
TPUL_SU
TPUL_HD
Data Valid
VDD = 0V
VDD = 3.3V
VDD Power On
SSC_CTL[1:0]
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