參數(shù)資料
型號: ICS84314AY-02LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/23頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER 700MHZ 32-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: HiPerClockS™
類型: 頻率合成器
PLL: 帶旁路
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無/是
頻率 - 最大: 700MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
其它名稱: 800-2281
84314AY-02LF
ICS84314AY-02LF-ND
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY
SYNTHESIZER w/FANOUT BUFFER
ICS84314-02
IDT / ICS 3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER
1
ICS84314AY-02 REV. A MARCH 24, 2009
General Description
The ICS84314-02 is a general purpose quad output
frequency synthesizer and a member of the
HiPerClockS family of High Performance Clock
Solutions from IDT. When the device uses parallel
loading, the M bits are programmable and the output
divider is hard-wired for divide by 2 thus providing a frequency
range of 125MHz to 350MHz. In serial programming mode, the M
bits are programmable and the output divider can be set for either
divide by 1, 2, 4 or divide by 8, providing a frequency range of
31.25MHz to 700MHz. Additionally, the device supports spread
spectrum clocking (SSC) for minimizing Electromagnetic Interfer-
ence (EMI). The low cycle-cycle jitter and broad frequency range
of the ICS84314-02 make it an ideal clock generator for a variety
of demanding applications which require high performance.
Features
Fully integrated PLL
Four differential 3.3V or 2.5V LVPECL output pairs
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK input
Output frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Parallel interface for programming M dividers
Supports Spread Spectrum Clocking (SSC)
Down spread: -0.6%
Serial 3 wire interface
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: 40ps (maximum)
Output duty cycle: 47% – 53%
Full 3.3V or mixed 3.3V core, 2.5V output operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS
ICS
OSC
VCO
PLL
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Output Divider N
÷1
÷2 (Power-up Default)
÷4
÷8
CONFIGURATION
INTERFACE
LOGIC
÷ M
0
1
0
1
÷ 16
PHASE DETECTOR
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
÷2
PU
PD
9
10 11 12 13 14 15 16
32 31 30
29 28
27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
M4
M5
M6
M7
M8
VEE
VCC
VCCO
TEST_CLK
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
VCCO
Q0
nQ0
Q1
nQ
1
Q2
nQ
2
Q3
nQ
3
M2
M1
M0
VCO_SEL
nP_LOAD
XTAL_OUT
XTAL_IN
M3
Block Diagram
Pin Assignment
ICS84314-02
32 Lead LQFP
Y Package
7mm x 7mm x 1.4mm package body
Top View
NOTE: Pullup (PU) and Pulldown (PD) refer to internal input resistors.
See Table 2, Pin Characteristics, for typical values.
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