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IDT / ICS 3.3V LVPECL CLOCK GENERATOR
9
ICS843022AG REV A AUGUST 1, 2006
ICS843022
FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 4A shows a schematic example of the ICS843022. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
output frequency. The C1 = 27pF and C2 = 33pF are
recommended for frequency accuracy. For different board layout,
the C1 and C2 values may be slightly adjusted for optimizing
frequency accuracy.
FIGURE 4A. ICS843022 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 4B shows an example of P.C. board layout. The crystal X1
footprint in this example allows either surface mount (HC49S) or
through hole (HC49) package. C3 is 0805. C1 and C2 are 0402.
Other resistors and capacitors are 0603. This layout assumes
that the board has clean analog power and ground planes.
FIGURE 4B. ICS843022 PC BOARD LAYOUT EXAMPLE
R5
133
VCC
+
-
VCC
R3
133
C1
27pF
C2
33pF
C5
0.1u
VCC
Zo = 50 Ohm
18pF
R6
82.5
X1
25MHz
C4
0.01u
U1
ICS843022
1
2
3
4
8
7
6
5
VCCA
VEE
XTAL_OUT
XTAL_IN
VCC
Q
nQ
FREQ_SEL
R1
1K
VCC=3.3V
R4
82.5
VCCA
Zo = 50 Ohm
C3
10uF
R2
10