- 您現在的位置：買賣IC網 > PDF目錄360768 > ICS843002I-41 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR PDF資料下載
參數資料
| 型號： | ICS843002I-41 |
| 英文描述： | 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| 中文描述： | 700MHz的，FEMTOCLOCKS，商標VCXO的基于SONET / SDH的抖動衰減器 |
| 文件頁數： | 11/21頁 |
| 文件大?。?/td> | 279K |
| 代理商： | ICS843002I-41 |
843002AKI-41
www.icst.com/products/hiperclocks.html
REV. A JUNE 1, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843002I-41
700MH
Z
, F
EMTO
C
LOCKS
VCXO B
ASED
SONET/SDH J
ITTER
A
TTENUATOR
PRELIMINARY
N
OTES
ON
S
ETTING
THE
V
ALUE
OF
C
P
As another general rule, the following relationship should be
maintained between components C
S
and C
P
in the loop filter:
C
establishes a second pole in the VCXO PLL loop filter. For
higher damping factors (> 1), calculate the value of C
based on
a C
value that would be used for a damping factor of 1. This will
minimize baseband peaking and loop instability that can lead to
output jitter.
C
also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A C
value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is high,
charge pump current is high, and C
is too small, the VCXO PLL
input voltage can hit the supply or ground rail resulting in non-
linear loop response.
The best way to set the value of C
is to use the filter response
software under development from ICS (please refer to the
following section). C
should be increased in value until it just
starts affecting the passband peak.
L
OOP
F
ILTER
R
ESPONSE
S
OFTWARE
Online tools to calculate loop filter response (coming soon) at
www.icst.com. Contact your local sales representative if a tool
cannot be found for this product.
N
OTES
ON
E
XTERNAL
C
RYSTAL
L
OAD
C
APACITORS
In the loop filter schematic diagram, capacitors are shown be-
tween pins 32 to ground and between pins 31 to ground. These
are optional crystal load capacitors which can be used to cen-
ter tune the external pullable crystal (the crystal frequency can
only be lowered by adding capacitance, it cannot be raised).
Note that the addition of external load capacitors will decrease
the crystal pull range and the Kvco value.
C
P
=
C
S
20
1
2
3
32 31
LF1
LF0
ISET
C
S
R
S
C
P
R
SET
The external crystal devices and loop filter components should
be kept close to the device. Loop filter and crystal PCB
connection traces should be kept short and well separated from
each other and from other signal traces. Other signal traces
should not run underneath the device, the loop filter or crystal
components.
E
XTERNAL
VCXO PLL C
OMPONENTS
In general, the loop damping factor should be 0.7 or greater to
ensure output stability. A higher damping factor will create less
peaking in the passband. A higher damping factor may also
increase lock time and output clock jitter when there is excess
digital noise in the system application, due to the reduced ability
of the PLL to respond to and therefore compensate for phase
noise ingress.
The LOR0 and LOR1 pins are controlled by the internal clock
activity monitor circuits. The clock activity monitor circuits are
clocked by the VCXO PLL phase detector feedback clock.
The LOR output is asserted high if there are three consecutive
feedback clock edges without any reference clock edges (in
both cases, either a negative or positive transition is counted
L
OSS
OF
R
EFERENCE
I
NDICATOR
(LOR0
AND
LOR1) O
UTPUT
P
INS
.
as an “edge”). The LOR output will otherwise be low. The
activity monitor does not flag excessive reference transitions in
an phase detector observation interval as an error. The monitor
only distinguishes between transitions occurring and no transi-
tions occurring.
相關PDF資料 |
PDF描述 |
|---|---|
| ICS843002 | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002AG | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002AGLF | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002AGLFT | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002AGT | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS843002I-72 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR |
| ICS843003 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843003AG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843003AGI-01 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843003AGI-01LF | 功能描述:IC SYNTHESIZER LVPECL 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。