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參數(shù)資料
| 型號(hào)： | ICS728MLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大小： | 0K |
| 描述： | IC VCXO 27MHZ 3.3V 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 壓控晶體振蕩器（VCXO） |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 27MHz |
| 除法器/乘法器： | 無(wú)/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱(chēng)： | 800-1098-6 |
ICS728
LOW COST 27 MHZ 3.3 VOLT VCXO
VCXO
IDT / ICS LOW COST 27 MHZ 3.3 VOLT VCXO
3
ICS728
REV D 051310
External Component Selection
The ICS728 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD (pin 2) and GND (pin 4), as close to these
pins as possible. For optimum device performance, the
decoupling capacitor should be mounted on the component
side of the PCB. Avoid the use of vias in the decoupling
circuit.
Series Termination Resistor
When the PCB trace between the clock output (CLK, pin 5)
and the load is over 1 inch, series termination should be
used. To series terminate a 50
trace (a commonly used
trace impedance) place a 33
resistor in series with the
clock line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20
.
Quartz Crystal
The ICS728 VCXO function consists of the external crystal
and the integrated VCXO oscillator circuit. To assure the
best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the following section shown must be
followed.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
ICS728 incorporates on-chip variable load capacitors that
“pull” (change) the frequency of the crystal. The crystal
specified for use with the ICS728 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
° C
±20 ppm
Temperature Stability
±30 ppm
Aging
±20 ppm
Load Capacitance
14 pf
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
250 Max
Equivalent Series Resistance
35
Max
The third overtone mode of the crystal and all spurs must be
>100 ppm distant from 3x the fundamental resonance
measured with a physical load of 14 pF.
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the ICS728. There should be no vias between the crystal
pins and the X1 and X2 device pins. There should be no
signal traces underneath or close to the crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on the
PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used and by PCB layout.
The typical required capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of your final
layout, a frequency counter capable of 1 ppm resolution and
accuracy, two power supplies, and some samples of the
crystals which you plan to use in production, along with
measured initial accuracy for each crystal at the specified
crystal load capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS728 to 3.3 V. Connect pin 3 of the
ICS728 to the second power supply. Adjust the voltage on
pin 3 to 0V. Measure and record the frequency of the CLK
output.
2. Adjust the voltage on pin 3 to 3.3 V. Measure and record
the frequency of the same output.
To calculate the centering error:
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal being
measured
If the centering error is less than ±25 ppm, no adjustment is
needed. If the centering error is more than 25 ppm negative,
the PC board has excessive stray capacitance and a new
PCB layout should be considered to reduce stray
Error
10
6x
f
3.0V
f
tet
arg
–
()
f
0V
f
tet
arg
–
()
+
f
tet
arg
------------------------------------------------------------------------------
error
xtal
–
=
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| ICS728MT | 功能描述:IC VCXO 3.3V 27MHZ 8-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類(lèi)型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱(chēng):23S08-5HPGG |
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