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參數(shù)資料
| 型號： | ICS413M |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 62K |
| 代理商： | ICS413M |
PC PERIPHERAL CLOCK
MDS 413 A
2
Revision 040202
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ICS413
Pin Assignment
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS413 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between each VDD and the PCB ground plane.
1
2
3
ICLK
4
14. 318/ 24. 576M
25M
GND
VDD
GND
24. 576M
8
7
6
5
VDD
8 Pi n ( 150 mi l ) SOI C
R (pin 6)
CLK Frequency
(output on pin 6)
Pull-up
14.318 MHz
Pull-down
24.576 MHz
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
Input
Clock connection. Connect to 14.31818 MHz clock.
2
VDD
Power
Connect to voltage supply.
3
GND
Power
Connect to ground.
4
24.576M
Output
24.576 MHz clock output.
5
25M
Output
25 MHz clock output.
6
14.318/24.576M
Input/
Output
Selectable 14.318/24.576 MHz clock output. No internal
pull-up or pull-down resistors.
7
GND
Power
Connect to ground.
8
VDD
Power
Connect to voltage supply.
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