參數(shù)資料
型號(hào)： ICS2002Y
元件分類： Codec
英文描述： Wavedec Digital Audio Codec
中文描述： Wavedec數(shù)字音頻編解碼器
文件頁(yè)數(shù)： 11/21頁(yè)
文件大?。?/td> 550K
代理商： ICS2002Y
Indirect Register Definitions
All writeable bits/registers are also readable. In addition, there
are some read only bits/registers, which are noted where appro-
priate.
Reserved bits should be written to zero, and read back zeros.
Reserved registers should not be written or read.
Except where noted, registers should be accessed as 8 bit
registers via address BASE+2.
General Purpose Registers
IR4E Register Access Mode Select
This register must be written to 01h for any other
indirect (or direct) accesses to occur, except for RA
writes, which always occur based on chip select. This
indirect address allows multiple companion chips to
share resources in a system (such as bus buffers, address
decodes, interrupts, and DMA channels).
This register is cleared only by hardware reset, and in
unaffected by MCR (see below).
IR80 Chip Control
Bits 7:3 - reserved
Bit 2 - Sound Source Emulation Mode (SSMODE)
This bit sets the chip to operate in Sound Source Emu-
lation mode. In Sound Source Emulation Mode, the two
address pins (SA1, SA0) are mapped to match the PC
parallel port as used by the Sound Source as follows:
Chip Address
0
1
2
3
Sound Source
Data
Status
Control
unused
IC2002
DH
Status
DL
RA
To use this mode, the chip must be configured before
the Sound Source compatible application is run (I/O
Mode DMA, DSP loaded and running, SR running,
etc.). Then, the
IC2002
is put in SSMODE and RA
(now at address 3) is written to 8Bh. In the PC, the BIOS
pointer to the parallel port is changed to the base address
of the
IC2002
chip, and the application can then be
started.
This bit is reset by MCR. Hence, it must be set after
MCR is set, on a second write to this register.
Bit 1 - Chip STAND ALONE Mode
This bit sets the chip to operate in STAND ALONE
mode. In STAND ALONE mode, the STATUS and RA
registers are accessible at BASE+0 and BASE+1. This
mode should be used to speed register access when the
ICS2002
is being used by itself, without other ICS
chips sharing resources (such as address decodes, inter-
rupts, DMA channels, bus buffers, etc.).
When bit 1 is zero, the
ICS2002
will operate in COM-
PANION mode. In this mode, the STATUS register is
mapped only to indirect address 83h. This is done to
avoid conflict with other ICS chips that will provide
STATUS and RA read back at the first two base ad-
dresses.
In addition, STAND ALONE mode configures the
DRQP, DRQR, and IRQ pins to operate as outputs, with
both one and zero levels being actively driven. When
in COMPANION mode, these pins have a strong source
for the high state and a weak sink for the low state to
allow wire-and connections to other ICS chips.
This bit is reset by hardware reset only, not by MCR.
Bit 0 - Master Chip Reset (MCR)
0 - Hold chip in reset
1 - Remove reset
This bit is cleared to zero by a hardware reset. Thus, any
functions reset by MCR are also reset by the RESET
pin.
ICS2002
11
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