參數(shù)資料
型號(hào)： ICS1894KI-40LFT
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 23/53頁(yè)
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 40QFN
標(biāo)準(zhǔn)包裝： 1
系列： PHYceiver™
類(lèi)型： PHY 收發(fā)器
規(guī)程： MII，RMII
電源電壓： 3.14 V ~ 3.47 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 40-VFQFPN（6x6）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 800-2032-6
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
3
ICS1894-40
REV K 022412
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
AMDIX
IN/Ipu
AMDIX Enable
2
TP_AP
AIO
Twisted pair port A (for either transmit or receive) positive signal
3
TP_AN
AIO
Twisted pair port A (for either transmit or receive) negative signal
4
VSS
Ground Connect to ground.
5
VDD
Power
3.3V Power Supply
6
TP_BN
AIO
Twisted pair port B (for either transmit or receive) negative signal
7
TP_BP
AIO
Twisted pair port B (for either transmit or receive) positive signal
8
VDD
Power
3.3V Power Supply
9
TCSR
AIO
Transmit Current bias pin, connected to Vdd and ground via two resistors.
10
VSS
Ground Connect to ground.
11
RESET_N
Input
Hardware reset for the whole chip (active low)
12
P2/INT
IO/Ipd
PHY address Bit 2 as input (during power on reset and hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
13
MDIO
IO
Management Data Input/Output
14
MDC
Input
Management Data Clock
15
VDDIO
Power
3.3 V IO Power Supply.
16
HWSW/
CRS
IO/Ipd
Hardware/Software control for phy speed as input (during power on reset and
hardware reset) and CRS output in MII mode.
17
Regpin/
COL
IO/Ipd
Full register access enable as input (during power on reset and hardware reset) and
COL output in MII mode
18
AMDIX/RXD3
IO/Ipu
AMDIX hardware enable as input (during power on reset and hardware reset)
Receive data Bit 3 as output in MII mode
19
P3/RXD2
IO/Ipd
PHY address Bit 3 as input (during power on reset and hardware reset)
Receive data Bit 2 as output in MII mode
20
RXTRI/
RXD1
IO/Ipd
RX isolate enable (during power on reset and hardware reset)
Received data Bit 1 as output in both RMII and MII modes
21
SI/LED4
IO/Ipd
MII/SI mode select as input (during power on reset and hardware reset) and
LED #4 as output
22
FDPX/
RXD0
IO/Ipu
Full duplex enable (during power on reset and hardware reset)
Received data Bit 0 as output in both RMII and MII modes.
23
RMII/RXDV
IO/Ipd
RMII/MII select as input (during power on reset and hardware reset)
Receive data valid in MII mode and CRS_DV in RMII mode as output
24
SPEED
Ipu
10/100M input select. 1 = 100M mode, 0 = 10M mode.
25
TXER
IN
TXER Input
26
ANSEL/
RXCLK9
IO/Ipu
Auto-negotiation enable(during power on reset and hardware reset)
Receive clock as output in MII mode
27
NOD/
RXER
IO/Ipd
Node/repeater select (during power on reset and hardware reset)
Receive error as output in MII mode
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